F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) 3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) 4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) x
3.1. Design Features 3.2. Hardware and Software Requirements 3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams 3.4. Design Parameters 3.5. Design Components 3.6. Design Software Flow 3.7. Clocking Scheme 3.8. Interface Signals 3.9. Hardware Setup 3.10. Design Limitation (AXI/CV)
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams x
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer) 3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer) 3.3.3. HDMI 2.1 RX-Only Retransmit Design Block Diagram 3.3.4. HDMI 2.1 TX-Only Retransmit Design Block Diagram
3.4. Design Parameters x
3.4.1. IP Parameters 3.4.2. Design Example Parameters
3.6. Design Software Flow x
3.6.1. Configure Redriver Setting 3.6.2. Initialize TX Path 3.6.3. Initialize RX Path 3.6.4. Initialize HDMI TX Register 3.6.5. Wait for RX Path Ready 3.6.6. TX Reconfiguration and Link Training 3.6.7. Set TX Video Clock 3.6.8. Set AXI2CV Configuration 3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme x
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON) 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF) 3.7.3. Clock Details
3.8. Interface Signals x
3.8.1. Platform Design System
3.9. Hardware Setup x
3.9.1. Supporting Additional Video Resolutions 3.9.2. Running the TX-Only Design 3.9.3. Running the RX-Only Design
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

3.4.2. Design Example Parameters

Table 26.  Available Design Examples
Parameter Value Description
Select Design Agilex™ 7 HDMI RX-TX Retransmit with AXI4-stream interface and video frame buffer Select the design example to be generated. The generated design example has pre-configured parameter settings. It does not follow user settings.

This design is applicable only when VIDEO IN AND OUT USE THE SAME CLOCK is not selected.

Agilex™ 7 HDMI RX-TX Retransmit with AXI4-stream interface without video frame buffer Select the design example to be generated. The generated design example has pre-configured parameter settings. It does not follow user settings.

This design is applicable only when VIDEO IN AND OUT USE THE SAME CLOCK is selected.

Agilex TX Design Only Select the design example to be generated. The generated design example has pre-configured parameter settings. It does not follow user settings.

This design is applicable only when DIRECTION is TX.

This design only generates with the video frame buffer (that is, VIDEO IN AND OUT USE THE SAME CLOCK is not selected.)

Agilex RX Design Only Select the design example to be generated. The generated design example has preconfigured parameter settings. It does not follow user settings.

This design is applicable only when DIRECTION is RX.

This design only generates with the video frame buffer (that is, VIDEO IN AND OUT USE THE SAME CLOCK is not selected.)

Select Daughter Card Revision 0: Revision 9

2: No Daughter Card

 Select available HDMI daughter card for Design Example generation.
Table 27.  Design Example Files
Parameter Value Description
Simulation On, Off Turn on this option to generate the necessary files for the simulation testbench.

Design example simulation is not supported if Include I2C is selected.

Synthesis On, Off Turn on this option to generate the necessary files for Quartus Prime compilation and hardware demonstration.
Table 28.  Generated HDL Format
Parameter Value Description
Generate File Format Verilog, VHDL Select your preferred HDL format for the generated design example fileset.
Note: This option determines only the format for the generated top level IP files. All other files (such as example testbenches and top level files for hardware demonstration) are in Verilog HDL format.
Table 29.  Target Development Kit
Parameter Value Description
Select Board No Development Kit,

Agilex™ 7 I-Series SoC FPGA Development Kit FA,

Agilex™ 7 I-Series SoC FPGA Development Kit FB,

Custom Development Kit

 Select the board for the targeted design example.
  • No Development Kit

    This option excludes all hardware aspects for the design example. The IP core sets all pin assignments to virtual pins.

  • Agilex™ 7 I-Series SoC FPGA Development Kit FA This option automatically selects the project’s target device to match the device on this development kit (AGIB027R31B1E1V).
  • Agilex™ 7 I-Series SoC FPGA Development Kit FB

    This option automatically selects the project’s target device to match the device on this development kit (AGIB027R31B1E1VAA).

  • Custom Development Kit

    This option allows the design example to be tested on a third party development kit with an Intel FPGA. You may need to set the pin assignments on your own.

Note: For Agilex™ 7 I-Series SoC FPGA Development Kit FA and Agilex™ 7 I-Series SoC FPGA Development Kit FB, you may change the target device using the Change Target Device parameter if your board revision has a different device variant. The IP core sets all pin assignments according to the development kit.
Table 30.  Target Device
Parameter Value Description
Change Target Device On, Off Turn on this option and select the preferred device variant for the development kit.
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