F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) 3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) 4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) x
3.1. Design Features 3.2. Hardware and Software Requirements 3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams 3.4. Design Parameters 3.5. Design Components 3.6. Design Software Flow 3.7. Clocking Scheme 3.8. Interface Signals 3.9. Hardware Setup 3.10. Design Limitation (AXI/CV)
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams x
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer) 3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer) 3.3.3. HDMI 2.1 RX-Only Retransmit Design Block Diagram 3.3.4. HDMI 2.1 TX-Only Retransmit Design Block Diagram
3.4. Design Parameters x
3.4.1. IP Parameters 3.4.2. Design Example Parameters
3.6. Design Software Flow x
3.6.1. Configure Redriver Setting 3.6.2. Initialize TX Path 3.6.3. Initialize RX Path 3.6.4. Initialize HDMI TX Register 3.6.5. Wait for RX Path Ready 3.6.6. TX Reconfiguration and Link Training 3.6.7. Set TX Video Clock 3.6.8. Set AXI2CV Configuration 3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme x
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON) 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF) 3.7.3. Clock Details
3.8. Interface Signals x
3.8.1. Platform Design System
3.9. Hardware Setup x
3.9.1. Supporting Additional Video Resolutions 3.9.2. Running the TX-Only Design 3.9.3. Running the RX-Only Design
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

3.4.1. IP Parameters

Table 24.  HDMI RX Direction
Parameter Value Description
DIRECTION Receiver Determines the selection for HDMI simplex RTL.
SUPPORT DEEP COLOR 1: On Determines if the core can decode deep color formats.
SUPPORT AUXILIARY 1: On Determines if the auxiliary channel decoding is included
SUPPORT AUDIO 1: On Determines if the core can decode audio.
PIXEL PER CLOCK 8 Supports 8 pixels per clock for Agilex™ 7 devices.
SUPPORT FRL 1: On For Agilex™ 7 devices, only Support FRL =1 is supported.
INCLUDE I2C MASTER/SLAVE 1: On Determines if the I2C slave block is included.
INCLUDE EDID RAM 1: On Determines if the EDID RAM block is included.
EDID RAM ADDR WIDTH 8 Log base 2 of the EDID RAM size.
RAM FILE PATH – Specifies the file path of your EDID content. File name must be in .hex or .mif format.

When you generate the RX design and you do not have EDID content, you can avoid the error message and proceed with the design example generation by creating an empty .hex file under your current working directory and insert that file name for this parameter.

When you have EDID content ready, you can open the HDMI RX IP (Project Navigator > IP components > nios_hdmi_rx) and regenerate HDMI RX with the valid EDID content.

ENABLE ACTIVE VIDEO PROTOCOL AXIS-VVP Full Determines the input video data format.
HDMI21_VARIANT
  • 0: TMDS only
  • 1: FRL and TMDS
 Determines the selection of HDMI variant.
Table 25.  HDMI TX Direction
Parameter Value Description
DIRECTION Transmitter Determines the selection for HDMI simplex RTL.
SUPPORT DEEP COLOR 1: On Determines if the core can encode deep color formats.
SUPPORT AUXILIARY 1: On Determines if the auxiliary channel encoding is included.
SUPPORT AUDIO 1: On Determines if the core can encode audio.
PIXEL PER CLOCK 8 Supports 8 pixels per clock for Agilex™ 7 devices.
SUPPORT FRL 1: On For Agilex™ 7 devices, only Support FRL =1 is supported.
INCLUDE I2C MASTER/SLAVE 1: On Determines if the I2C master block is included.
ENABLE ACTIVE VIDEO PROTOCOL AXIS-VVP Full Determines the input video data format.
VIDEO IN AND OUT USE THE SAME CLOCK 1: On Set to ON for HDMI 2.1 RX-TX retransmit without video frame buffer design.
0: Off Set to OFF for HDMI 2.1 RX-TX direct retransmit with video frame buffer design.
HDMI21_VARIANT
  • 0: TMDS only
  • 1: FRL and TMDS
 Determines the selection of HDMI variant.
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