F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) 3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) 4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) x
3.1. Design Features 3.2. Hardware and Software Requirements 3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams 3.4. Design Parameters 3.5. Design Components 3.6. Design Software Flow 3.7. Clocking Scheme 3.8. Interface Signals 3.9. Hardware Setup 3.10. Design Limitation (AXI/CV)
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams x
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer) 3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer)
3.4. Design Parameters x
3.4.1. HDMI RX Direction 3.4.2. HDMI TX Direction
3.6. Design Software Flow x
3.6.1. Configure Redriver Setting 3.6.2. Initialize TX Path 3.6.3. Initialize RX Path 3.6.4. Initialize HDMI TX Register 3.6.5. Wait for RX Path Ready 3.6.6. TX Reconfiguration and Link Training 3.6.7. Set TX Video Clock 3.6.8. Set AXI2CV Configuration 3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme x
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON) 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF) 3.7.3. Clock Details
3.8. Interface Signals x
3.8.1. Platform Design System
3.9. Hardware Setup x
3.9.1. Supporting Additional Video Resolutions
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

1.2. Generating the Design

Use the HDMI Intel® FPGA IP parameter editor in the Quartus® Prime software to generate the design examples.

Starting with the Nios® V Embedded Design Suite (EDS) in the Quartus® Prime Pro Edition software version 19.2 and Quartus® Prime Standard Edition software version 19.1, Intel has removed the Cygwin component in the Windows* version of Nios® V EDS, replacing it with Windows Subsytem for Linux (WSL). If you are a Windows user, you need to install WSL prior to generating your design example.

Starting with the Quartus® Prime Pro Edition software version 24.1, you need to install Cmake version 3.14.2 onward prior to generating your design example. Cmake is needed for software generation and rebuilding.
Note: You need a Nios® V evaluation license. Refer to the Nios® V Processor Licensing topic in the Nios® V Embedded Processor Design Handbook.
Figure 3. Generating the Design Flow
  1. Create a project targeting the Agilex™ 7 device family with F-Tile, and select the desired device.
  2. In the IP Catalog, locate and double-click HDMI Intel FPGA IP. The New IP Variant or New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  4. Click OK. The parameter editor appears.
  5. On the IP tab, configure the desired parameters for both TX or RX. Common parameters will be applied to both TX and RX.
  6. Support FRL is turned on by default to generate the HDMI 2.1 design example in FRL mode.
  7. On the Design Example tab, select Agilex™ 7 HDMI RX-TX Retransmit with clocked video interface.
  8. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example.

    You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.

    Generation time for Synthesis will take about 30 minutes to allow ipgen.tcl process to qsys-generate a large number of PHY reconfig profiles and remove unused PHY SDC constraints, and speed up Fitter compilation time.

  9. For Generate File Format, select Verilog or VHDL.
  10. For Select Board, select the relevant development kit. You can change the target device using Change Target Device parameter if your board revision does not match the grade of the default targeted device. For Agilex™ I-Series SoC Development Kit FA board, the target device is set to AGIB027R31B1E1V. For Agilex™ I-Series SoC Development Kit FB board, the target device is set to AGIB027R31B1E1VAA.
  11. Click Generate Example Design.
    Table 4.  Design Example Variant Generation
    Enable Active Video Protocol Video in and out use the same clock Design Example Variant
    None Not Applicable HDMI 2.1 RX-TX retransmit design on clocked video interface
    AXIS-VVP Full No HDMI 2.1 RX-TX retransmit design with video frame buffer on AXI4-stream interface
    AXIS-VVP Full Yes HDMI 2.1 RX-TX retransmit design without video frame buffer on AXI4-stream interface
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