HDMI Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

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ID 709314
Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. Document Revision History for the HDMI Agilex F-tile Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.5.2.1. RX PHY Adapter x
2.5.2.1.1. FRL
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. Document Revision History for the HDMI Agilex F-tile Design Example User Guide

2.5.3. Top-Level Common Blocks

The top-level common blocks include the transceiver arbiter, the RX-TX link components, and the CPU subsystem.
Table 12.  Top-Level Common Blocks
Module Description
RX-TX Link
  • The video data output and synchronization signals from HDMI RX core loop through a DCFIFO across the RX and TX video clock domains.
  • The auxiliary data port of the HDMI TX core controls the auxiliary data that flow through the DCFIFO through backpressure. The backpressure ensures there is no incomplete auxiliary packet on the auxiliary data port.
  • This block also performs external filtering:
    • Filters the audio data and audio clock regeneration packet from the auxiliary data stream before transmitting to the HDMI TX core auxiliary data port.
    • Filters the High Dynamic Range (HDR) InfoFrame from the HDMI RX auxiliary data and inserts an example HDR InfoFrame to the auxiliary data of the HDMI TX through the Avalon® streaming multiplexer.
CPU Subsystem

The CPU subsystem functions as SCDC and DDC controllers, and source reconfiguration controller.

  • The source SCDC controller contains the I2C master controller. The I2C master controller transfers the SCDC data structure from the FPGA source to the external sink for HDMI 2.0 operation. For example, if the outgoing data stream is 6,000 Mbps, the Nios® II processor commands the I2C master controller to update the TMDS_BIT_CLOCK_RATIO and SCRAMBLER_ENABLE bits of the sink TMDS configuration register to 1.
  • The same I2C master also transfers the DDC data structure (E-EDID) between the HDMI source and external sink.
  • The Nios® II CPU acts as the reconfiguration controller for the HDMI source. The CPU relies on the periodic rate detection from the RX Reconfiguration Management module to determine if the TX requires reconfiguration. The Avalon® memory-mapped slave translator provides the interface between the Nios® II processor Avalon® memory-mapped master interface and the Avalon® memory-mapped slave interfaces of the externally instantiated HDMI source’s IOPLL and TX PMA Direct PHY.
  • Perform link training through I2C master interface with external sink
IOPLL (vid_clk)
  • The IOPLL performs the following:
    • Generates the video clock. The reference clock to this IOPLL is 100MHZ clock.
    • Provides fix clock frequency which is 225MHZ.
F-tile System Clock

This IP connects the System PLL output clock as well as the Tx PLL and Rx CDR reference clock to the F-tile PMA/FEC Direct PHY IP.

System PLL clock output shall always set to run at a higher clock frequency than the native PMA recovered clock.

For this design, the clock frequency is 900MHZ
Level Two Title