HDMI Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

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ID 709314
Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. Document Revision History for the HDMI Agilex F-tile Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.5.2.1. RX PHY Adapter x
2.5.2.1.1. FRL
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. Document Revision History for the HDMI Agilex F-tile Design Example User Guide

2.6. Design Software Flow

In the design main software flow, the Nios® II processor configures the TI redriver setting and initializes the TX and RX paths upon power-up.
Figure 13. Software Flow in main.c Script
The software executes a while loop to monitor sink and source changes, and to react to the changes. The software may trigger TX reconfiguration, TX link training and start transmitting video.
Note: Refer to the following figures for the detail flow:
  1. Initialize TX Path : Figure 14.
  2. Initialize RX Path: Figure 15.
  3. TX Reconfiguration and Link Training: Figure 16.
  4. HDMI TX Transmit Video: Figure 18.
Figure 14. TX Path Initialization Flowchart
Figure 15. RX Path Initialization Flowchart
Figure 16. TX Reconfiguration and Link Training Flowchart
Figure 17. Link Training LTS:3 Process at Specific FRL Rate Flowchart
Note: Refer to Figure 17 for more detail about Perform LTS: 3 Process at Specific FRL Rate.
Figure 18. HDMI TX Video Transmission Flowchart
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