AN 952: Intel® Arria® 10 HDMI 2.1 System Design Guidelines

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ID 709310
Date 6/29/2021
Public

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Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Scope of System Design Guidelines 4. System Design Guide Requirements 5. HDMI 2.1 Compliance Test Specification 6. Future System Level Optimization 7. Document Revision History for AN 952: Intel Arria 10 HDMI 2.1 System Design Guidelines
4. System Design Guide Requirements x
4.1. Enabling PCB panel design 4.2. PCB Best Practice 4.3. System Link Budgeting Recommendation
4.3. System Link Budgeting Recommendation x
4.3.1. FPGA TX Settings 4.3.2. FPGA RX Settings
5. HDMI 2.1 Compliance Test Specification x
5.1. Protocol IP Compliance Test Specification 5.2. Electrical Compliance Test Specification 5.3. Gaps and Resolution
6. Future System Level Optimization x
6.1. Availability of Redrivers/Retimers 6.2. Agilex Platform
1. Terms and Acronyms
2. Introduction
3. Scope of System Design Guidelines
4. System Design Guide Requirements
5. HDMI 2.1 Compliance Test Specification
6. Future System Level Optimization
7. Document Revision History for AN 952: Intel Arria 10 HDMI 2.1 System Design Guidelines

1. Terms and Acronyms

Updated for:
Intel® Quartus® Prime Design Suite 21.2
Table 1.  Acronyms
Term Definition
ALA Advance Link Analyzer
ATXPLL ATX Phase Lock Loop
BUj Bounded Uncorrelated Jitter
CTS Compliance Test Suite
DDC Display Data Channel
Dj Deterministic Jitter
ESD Electrostatic Discharge
FMC FPGA Mezzanine Connector
FPLL Fractional Phase Lock Loop
FR4 PCB dielectric material
FRL Fixed Rate Link
PCA Power over Cable Assembly
PCB Printed Circuit Board
PJ Periodic Jitter
QSF Quartus Settings File
Rj Random Jitter
Rogers PCB dielectric material
SDG System Design Guidelines
SJ Sinusoidal Jitter
TI Texas Instruments
TMDS Transition Minimized Differential Signaling
TP1 Test Point 1
TTK Transceiver Toolkit
TTM Time to Market
Vpp Peak to Peak Voltage
WCM Worsecase Cable Model
Z Impedance
Level Two Title

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