AN 952: Intel® Arria® 10 HDMI 2.1 System Design Guidelines

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ID 709310
Date 6/29/2021
Public

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Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Scope of System Design Guidelines 4. System Design Guide Requirements 5. HDMI 2.1 Compliance Test Specification 6. Future System Level Optimization 7. Document Revision History for AN 952: Intel Arria 10 HDMI 2.1 System Design Guidelines
4. System Design Guide Requirements x
4.1. Enabling PCB panel design 4.2. PCB Best Practice 4.3. System Link Budgeting Recommendation
4.3. System Link Budgeting Recommendation x
4.3.1. FPGA TX Settings 4.3.2. FPGA RX Settings
5. HDMI 2.1 Compliance Test Specification x
5.1. Protocol IP Compliance Test Specification 5.2. Electrical Compliance Test Specification 5.3. Gaps and Resolution
6. Future System Level Optimization x
6.1. Availability of Redrivers/Retimers 6.2. Agilex Platform
1. Terms and Acronyms
2. Introduction
3. Scope of System Design Guidelines
4. System Design Guide Requirements
5. HDMI 2.1 Compliance Test Specification
6. Future System Level Optimization
7. Document Revision History for AN 952: Intel Arria 10 HDMI 2.1 System Design Guidelines

4.3. System Link Budgeting Recommendation

Platform link budgeting helps improve your experience by allocating sufficient loss on main board (with Intel® Arria® 10 FPGA), PCB panel or daughtercard and HDMI connector (including cables).

Apply a generic redriver primarily to meet Insertion Loss at 12 Gbps. Cable loss estimated at 18dB includes 2 connector, in a typical use case scenario.

Table 5.  Link Budgeting Distribution
Item Link Component Insertion Loss @12 Gbps Comment
1 FPGA → FMC → TX Redriver 5dB TX FFE recommended
2 Redriver → HDMI connector 10dB (+18dB)

Minimize lowest loss

Budgets for cable loss
3 HDMI cable → Connector → RX Redriver → FPGA RX (18dB+)10 dB

Better Redriver/retimer
Note: Refer to Table 7 for jitter tolerance data.

Section Content
FPGA TX Settings
FPGA RX Settings

Level Two Title