F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 4/29/2024
Document Table of Contents

3.1.3. System PLL

The F-Tile JESD204C Intel® FPGA IP supports system PLL clocking mode. If the frequency of a system PLL clock divided by 2 is greater than data rate divided by 64, a data_valid signal between MAC and F-Tile periodically asserts to sustain the bandwidth. For TX IP, this operation is handled through the custom cadence controller.