F-Tile JESD204C IP Release Notes

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ID 683862
Date 9/04/2025
Public

1.3. F-Tile JESD204C Intel® FPGA IP v4.0.0

Table 3.  v4.0.0 2024.11.25
Quartus® Prime Version Description Impact
24.3
  • Removed Enable internal serial loopback parameter from the Example Design tab.
  • Added Enable error injection parameter in the Example Design tab.
  • Added TX alarm initial value.
  • Enhanced Device Initialization Clock configuration in the Example Design tab.
  • Target Development Kit name change from Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit to Agilex™ 7 FPGA I-Series Transceiver-SOC Development Kit (Production 1 4x F-Tile) in the Example Design tab.
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