F-Tile JESD204C Intel® FPGA IP Release Notes

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ID 683862
Date 4/05/2024
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1. F-Tile JESD204C Intel® FPGA IP Release Notes 2. JESD204C Intel® FPGA IP User Guide Archives
1. F-Tile JESD204C Intel® FPGA IP Release Notes x
1.1. F-Tile JESD204C Intel® FPGA IP v2.2.0 1.2. F-Tile JESD204C Intel® FPGA IP v2.1.0 1.3. F-Tile JESD204C Intel® FPGA IP v2.0.2 1.4. F-Tile JESD204C Intel® FPGA IP v2.0.0 1.5. F-Tile JESD204C Intel® FPGA IP v1.1.0 1.6. F-Tile JESD204C Intel® FPGA IP v1.0.0
1. F-Tile JESD204C Intel® FPGA IP Release Notes
2. JESD204C Intel® FPGA IP User Guide Archives

1.5. F-Tile JESD204C Intel® FPGA IP v1.1.0

Table 5.  v1.1.0 2022.06.21
Quartus® Prime Version Description Impact
22.2
  • Updated PHY adapter naming.
  • Added system PLL clock (j204c_syspll_div2_clk) to the top-level transmitter and receiver IP core signals.
  • Fixed the L=6,12 parameter selection.
  • Fixed the FCLK_MULP=2 timing violation.
  • Fixed critical warnings in the Example Design.
  • Enabled hardware board selection for the Example Design in the IP Parameter Editor.
  • Enabled preset value for the Example Design in the IP Parameter Editor.
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