AN 953: Partially Reconfiguring a Design: on an Intel Agilex® 7 FPGA Development Board

ID 683849
Date 1/30/2024

Reference Design Files

The reference design files required for this tutorial are available in the following location:

To download the files:
  1. Click Code > Download ZIP.
  2. Unzip the file.
  3. Navigate to the appropriate sub-folder to access the reference designs for your target device:
    • tutorials/agilex7f_pcie_devkit_blinking_led
    • tutorials/agilex7m_pcie_devkit_blinking_led
Table 1.  Reference Design Files
File Name Description

Top-level file containing the flat implementation of the design. This module instantiates the blinking_led sub-partition and the top_counter module. Top-level 32-bit counter that controls LED[1] directly. The registered output of the counter controls LED[0], and also powers LED[2] and LED[3] via the blinking_led module.

Defines the timing constraints for the project. This module acts as the PR partition. The module receives the registered output of top_counter module, which controls LED[2] and LED[3].

Intel® Quartus® Prime project file containing the list of all the revisions in the project.


Intel® Quartus® Prime settings file containing the assignments and settings for the project.


The pr folder contains the complete set of files you create using this application note. Refer to these files at any point during the walkthrough.

Figure 2. Reference Design Files