Intel® FPGA SDK for OpenCL™ Pro Edition: Programming Guide

Download
ID 683846
Date 12/19/2022
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. Intel® FPGA SDK for OpenCL™ Overview 2. Intel® FPGA SDK for OpenCL™ Offline Compiler Kernel Compilation Flows 3. Obtaining General Information on Software, Compiler, and Custom Platform 4. Managing an FPGA Board 5. Structuring Your OpenCL Kernel 6. Designing Your Host Application 7. Compiling Your OpenCL Kernel 8. Emulating and Debugging Your OpenCL Kernel 9. Developing OpenCL Applications Using Third-party IDEs 10. Developing OpenCL™ Applications Using Intel® Code Builder for OpenCL™ 11. Intel® FPGA SDK for OpenCL™ Advanced Features A. Support Statuses of OpenCL Features B. Intel FPGA SDK for OpenCL Pro Edition Programming Guide Archives C. Document Revision History of the Intel® FPGA SDK for OpenCL™ Pro Edition Programming Guide
1. Intel® FPGA SDK for OpenCL™ Overview x
1.1. Intel® FPGA SDK for OpenCL™ Pro Edition Programming Guide Prerequisites 1.2. Intel® FPGA SDK for OpenCL™ FPGA Programming Flow
2. Intel® FPGA SDK for OpenCL™ Offline Compiler Kernel Compilation Flows x
2.1. One-Step Compilation for Simple Kernels 2.2. Multistep Intel® FPGA SDK for OpenCL™ Pro Edition Design Flow
3. Obtaining General Information on Software, Compiler, and Custom Platform x
3.1. Displaying the Software Version (version) 3.2. Displaying the Compiler Version (-version) 3.3. Listing the Intel® FPGA SDK for OpenCL™ Utility Command Options (help) 3.4. Listing the Intel® FPGA SDK for OpenCL™ Offline Compiler Command Options (no argument, -help, or -h) 3.5. Listing the Available FPGA Boards and Custom Platforms (-list-boards and -list-board-packages) 3.6. Displaying the Compilation Environment of an OpenCL Binary (env)
3.3. Listing the Intel® FPGA SDK for OpenCL™ Utility Command Options (help) x
3.3.1. Displaying Information on an Intel® FPGA SDK for OpenCL™ Utility Command Option (help <command_option>)
4. Managing an FPGA Board x
4.1. Installing an FPGA Board (install) 4.2. Uninstalling an FPGA Board (uninstall) 4.3. Querying the Device Name of Your FPGA Board (diagnose) 4.4. Running a Board Diagnostic Test (diagnose <device_name>) 4.5. Programming the FPGA Offline or without a Host (program <device_name>) 4.6. Programming the Flash Memory (flash <device_name>)
5. Structuring Your OpenCL Kernel x
5.1. Guidelines for Naming the Kernel 5.2. Programming Strategies for Optimizing Data Processing Efficiency 5.3. Programming Strategies for Optimizing Pointer-to-Local Memory Size 5.4. Implementing the Intel® FPGA SDK for OpenCL™ Channels Extension 5.5. Implementing OpenCL Pipes 5.6. Implementing Arbitrary Precision Integers 5.7. Using Predefined Preprocessor Macros in Conditional Compilation 5.8. Declaring __constant Address Space Qualifiers 5.9. Including Structure Data Types as Arguments in OpenCL Kernels 5.10. Inferring a Register 5.11. Enabling Double Precision Floating-Point Operations 5.12. Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels 5.13. Integer Promotion Rules
5.2. Programming Strategies for Optimizing Data Processing Efficiency x
5.2.1. Unrolling a Loop (unroll Pragma) 5.2.2. Disabling Pipelining of a Loop (disable_loop_pipelining Pragma) 5.2.3. Coalescing Nested Loops 5.2.4. Fusing Adjacent Loops (loop_fuse Pragma) 5.2.5. Marking Loops to Prevent Automatic Fusion (nofusion Pragma) 5.2.6. Specifying a Loop Initiation interval (II) 5.2.7. Loop Concurrency (max_concurrency Pragma) 5.2.8. Loop Speculation (speculated_iterations Pragma) 5.2.9. Loop Interleaving Control (max_interleaving Pragma) 5.2.10. Floating Point Optimizations (fp contract and fp reassociate Pragma) 5.2.11. Specifying Work-Group Sizes 5.2.12. Specifying Number of Compute Units 5.2.13. Specifying Number of SIMD Work-Items 5.2.14. Specifying the private_copies Memory Attribute 5.2.15. Specifying the use_stall_enable_clusters Cluster-control Attribute
5.4. Implementing the Intel® FPGA SDK for OpenCL™ Channels Extension x
5.4.1. Overview of the Intel® FPGA SDK for OpenCL™ Channels Extension 5.4.2. Channel Data Behavior 5.4.3. Multiple Work-Item Ordering for Channels 5.4.4. Restrictions in the Implementation of Intel® FPGA SDK for OpenCL™ Channels Extension 5.4.5. Enabling the Intel® FPGA SDK for OpenCL™ Channels for OpenCL Kernel
5.4.3. Multiple Work-Item Ordering for Channels x
5.4.3.1. Work-Item Serial Execution of Channels
5.4.5. Enabling the Intel® FPGA SDK for OpenCL™ Channels for OpenCL Kernel x
5.4.5.1. Declaring the Channel Handle 5.4.5.2. Implementing Blocking Channel Writes 5.4.5.3. Implementing Blocking Channel Reads 5.4.5.4. Implementing I/O Channels Using the io Channels Attribute 5.4.5.5. Emulating I/O Channels 5.4.5.6. Use Models of Intel® FPGA SDK for OpenCL™ Channels Implementation 5.4.5.7. Implementing Buffered Channels Using the depth Channels Attribute 5.4.5.8. Enforcing the Order of Channel Calls
5.5. Implementing OpenCL Pipes x
5.5.1. Overview of the OpenCL Pipe Functions 5.5.2. Pipe Data Behavior 5.5.3. Multiple Work-Item Ordering for Pipes 5.5.4. Restrictions in OpenCL Pipes Implementation 5.5.5. Enabling OpenCL Pipes for Kernels 5.5.6. Direct Communication with Kernels via Host Pipes
5.5.3. Multiple Work-Item Ordering for Pipes x
5.5.3.1. Work-item Serial Execution of Pipes
5.5.5. Enabling OpenCL Pipes for Kernels x
5.5.5.1. Ensuring Compatibility with Other OpenCL SDKs 5.5.5.2. Declaring the Pipe Handle 5.5.5.3. Implementing Pipe Writes 5.5.5.4. Implementing Pipe Reads 5.5.5.5. Implementing Buffered Pipes Using the depth Attribute 5.5.5.6. Implementing I/O Pipes Using the io Attribute 5.5.5.7. Enforcing the Order of Pipe Calls
5.5.6. Direct Communication with Kernels via Host Pipes x
5.5.6.1. Optional intel_host_accessible Kernel Argument Attribute 5.5.6.2. API Functions for Interacting with cl_mem Pipe Objects Bound to Host-Accessible Pipe Kernel Arguments 5.5.6.3. Creating a Host Accessible Pipe 5.5.6.4. Example Use of the cl_intel_fpga_host_pipe Extension
5.9. Including Structure Data Types as Arguments in OpenCL Kernels x
5.9.1. Matching Data Layouts of Host and Kernel Structure Data Types 5.9.2. Disabling Insertion of Data Structure Padding 5.9.3. Specifying the Alignment of a Struct
5.10. Inferring a Register x
5.10.1. Inferring a Shift Register
5.12. Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels x
5.12.1. Programming Strategies for Inferring the Accumulator
6. Designing Your Host Application x
6.1. Host Programming Requirements 6.2. Allocating OpenCL Buffers for Manual Partitioning of Global Memory 6.3. Triggering Collection Profiling Data During Kernel Execution 6.4. Accessing Custom Platform-Specific Functions 6.5. Modifying Host Program for Structure Parameter Conversion 6.6. Managing Host Application 6.7. Allocating Shared Memory for OpenCL Kernels Targeting SoCs 6.8. Sharing Multiple Devices Across Multiple Host Programs
6.1. Host Programming Requirements x
6.1.1. Host Machine Memory Requirements 6.1.2. Host Binary Requirement 6.1.3. Multiple Host Threads 6.1.4. Out-of-order Command Queues 6.1.5. Requirement for Multiple Command Queues to Execute Kernels Concurrently
6.2. Allocating OpenCL Buffers for Manual Partitioning of Global Memory x
6.2.1. Partitioning Buffers Across Multiple Interfaces of the Same Memory Type 6.2.2. Partitioning Buffers Across Different Memory Types (Heterogeneous Memory) 6.2.3. Creating a Pipe Object in Your Host Application 6.2.4. Enabling All Global Memory
6.3. Triggering Collection Profiling Data During Kernel Execution x
6.3.1. Profiling Autorun Kernels 6.3.2. Profile Data Acquisition
6.3.1. Profiling Autorun Kernels x
6.3.1.1. Multiple Autorun Profiling Calls
6.6. Managing Host Application x
6.6.1. Displaying Example Makefile Fragments (example-makefile or makefile) 6.6.2. Compiling and Linking Your Host Application 6.6.3. Using OpenCL ICD Extension APIs 6.6.4. Programming an FPGA via the Host 6.6.5. Termination of the Runtime Environment and Error Recovery
6.6.2. Compiling and Linking Your Host Application x
6.6.2.1. Linking Your Host Application to the Khronos ICD Loader Library 6.6.2.2. Displaying Flags for Compiling Host Application (compile-config) 6.6.2.3. Displaying Paths to OpenCL Host Runtime and MMD Libraries (ldflags) 6.6.2.4. Listing OpenCL Host Runtime and MMD Libraries (ldlibs) 6.6.2.5. Displaying Information on OpenCL Host Runtime and MMD Libraries (link-config or linkflags)
6.6.4. Programming an FPGA via the Host x
6.6.4.1. Programming Multiple FPGA Devices
7. Compiling Your OpenCL Kernel x
7.1. Compiling Your Kernel to Create Hardware Configuration File 7.2. Compiling Your Kernel without Building Hardware (-c) 7.3. Compiling and Linking Your Kernels or Object Files without Building Hardware (-rtl) 7.4. Specifying the Location of Header Files (-I=<directory>) 7.5. Specifying the Name of an Intel® FPGA SDK for OpenCL™ Offline Compiler Output File (-o <filename>) 7.6. Compiling a Kernel for a Specific FPGA Board and Custom Platform (-board=<board_name>) and (-board-package=<board_package_path>) 7.7. Resolving Hardware Generation Fitting Errors during Kernel Compilation (-high-effort) 7.8. Specifying Schedule Fmax Target for Kernels (-clock=<clock_target>) 7.9. Defining Preprocessor Macros to Specify Kernel Parameters (-D<macro_name>) 7.10. Generating Compilation Progress Report (-v) 7.11. Displaying the Estimated Resource Usage Summary On-Screen (-report) 7.12. Suppressing Warning Messages from the Intel® FPGA SDK for OpenCL™ Offline Compiler (-W) 7.13. Converting Warning Messages from the Intel® FPGA SDK for OpenCL™ Offline Compiler into Error Messages (-Werror) 7.14. Removing Debug Data from Compiler Reports and Source Code from the .aocx File (-g0) 7.15. Disabling Burst-Interleaving of Global Memory (-no-interleaving=<global_memory_type>) 7.16. Forcing Ring Interconnect for Global Memory (-global-ring) 7.17. Forcing a Single Store Ring to Reduce Area at the Expense of Write Throughput to Global Memory (-force-single-store-ring) 7.18. Forcing Fewer Read Data Reorder Units to Reduce Area at the Expense of Read Throughput to Global Memory (-num-reorder) 7.19. Configuring Constant Memory Cache Size (-const-cache-bytes=<N>) 7.20. Relaxing the Order of Floating-Point Operations (-ffp-reassociate) 7.21. Reducing Floating-Point Rounding Operations (-ffp-contract=fast) 7.22. Speeding Up Your OpenCL Compilation (-fast-compile) 7.23. Compiling Your Kernel Incrementally (-incremental) 7.24. Compiling Your Kernel with Memory Error Correction Coding (-ecc) 7.25. Disabling Hardware Kernel Invocation Queue (-no-hardware-kernel-invocation-queue) 7.26. Modifying the Handshaking Protocol (-hyper-optimized-handshaking) 7.27. Pipelining Loops in Non-task Kernels (-auto-pipeline)
7.23. Compiling Your Kernel Incrementally (-incremental) x
7.23.1. The Incremental Compile Report 7.23.2. Additional Command Options for Incremental Compilation 7.23.3. Limitations of the Incremental Compilation Feature
8. Emulating and Debugging Your OpenCL Kernel x
8.1. Setting up the Emulator 8.2. Modifying Channels Kernel Code for Emulation 8.3. Compiling a Kernel for Emulation (-march=emulator) 8.4. Emulating Your OpenCL Kernel 8.5. Debugging Your OpenCL Kernel on Linux 8.6. Limitations of the Intel® FPGA SDK for OpenCL™ Emulator 8.7. Discrepancies in Hardware and Emulator Results 8.8. Emulator Environment Variables 8.9. Extensions Supported by the Emulator 8.10. Emulator Known Issues
8.2. Modifying Channels Kernel Code for Emulation x
8.2.1. Emulating a Kernel that Passes Pipes or Channels by Value 8.2.2. Emulating Channel Depth 8.2.3. Emulating Applications with a Channel That Reads or Writes to an I/O Channel
9. Developing OpenCL Applications Using Third-party IDEs x
9.1. FPGA Workflows in Microsoft Visual Studio 9.2. FPGA Workflows in Eclipse 9.3. Limitations
9.1. FPGA Workflows in Microsoft Visual Studio x
9.1.1. Preparing the Visual Studio Environment 9.1.2. Creating an FPGA OpenCL Template 9.1.3. Configuring the Build Targets 9.1.4. Configuring Build Options for a Project 9.1.5. Generating the High-level Design Report 9.1.6. Building and Running the FPGA Template
9.2. FPGA Workflows in Eclipse x
9.2.1. Preparing the Eclipse Environment 9.2.2. Creating a Simple FPGA application 9.2.3. Creating a Makefile Project 9.2.4. Building a Project
9.2.2. Creating a Simple FPGA application x
9.2.2.1. Creating a Project 9.2.2.2. Reviewing the Code and Building the Project 9.2.2.3. Running the Application
10. Developing OpenCL™ Applications Using Intel® Code Builder for OpenCL™ x
10.1. Configuring the Intel® Code Builder for OpenCL™ Offline Compiler Plug-in for Microsoft Visual Studio 10.2. Configuring the Intel® Code Builder for OpenCL™ Offline Compiler Plug-in for Eclipse 10.3. Creating a Session in the Intel® Code Builder for OpenCL™ 10.4. Configuring a Session
11. Intel® FPGA SDK for OpenCL™ Advanced Features x
11.1. OpenCL Library 11.2. Memory Attributes for Configuring Kernel Memory Systems 11.3. Kernel Attributes for Reducing the Overhead on Hardware Usage 11.4. Kernel Replication Using the num_compute_units(X,Y,Z) Attribute 11.5. Intra-Kernel Registered Assignment Built-In Function
11.1. OpenCL Library x
11.1.1. Creating Library Objects From OpenCL Code 11.1.2. Understanding RTL Modules and the OpenCL Pipeline 11.1.3. Packaging an OpenCL Helper Function File for an OpenCL Library 11.1.4. Packaging an RTL Component for an OpenCL Library 11.1.5. Verifying the RTL Modules 11.1.6. Specifying an OpenCL Library when Compiling an OpenCL Kernel 11.1.7. Debugging Your OpenCL Library Through Simulation (Preview) 11.1.8. Using an OpenCL Library that Works with Simple Functions (Example 1) 11.1.9. Using an OpenCL Library that Works with External Memory (Example 2) 11.1.10. OpenCL Library Command-Line Options
11.1.1. Creating Library Objects From OpenCL Code x
11.1.1.1. Creating an Object File From OpenCL Code 11.1.1.2. Packaging Object Files into a Library File
11.1.2. Understanding RTL Modules and the OpenCL Pipeline x
11.1.2.1. Overview: Intel FPGA SDK for OpenCL Pipeline Approach 11.1.2.2. Integration of an RTL Module into the Intel FPGA SDK for OpenCL Pipeline 11.1.2.3. Stall-Free RTL 11.1.2.4. RTL Module Interfaces 11.1.2.5. Avalon Streaming Interface 11.1.2.6. RTL Reset and Clock Signals 11.1.2.7. Object Manifest File Syntax of an RTL Module 11.1.2.8. Interaction between RTL Module and External Memory 11.1.2.9. Order of Threads Entering an RTL Module 11.1.2.10. OpenCL C Model of an RTL Module 11.1.2.11. Potential Incompatibility between RTL Modules and Partial Reconfiguration
11.1.2.6. RTL Reset and Clock Signals x
11.1.2.6.1. Intel® Stratix® 10 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Modules
11.1.2.7. Object Manifest File Syntax of an RTL Module x
11.1.2.7.1. XML Elements for ATTRIBUTES 11.1.2.7.2. XML Elements for INTERFACE 11.1.2.7.3. XML Elements for RESOURCES
11.1.4. Packaging an RTL Component for an OpenCL Library x
11.1.4.1. Restrictions and Limitations in RTL Support for the Intel® FPGA SDK for OpenCL™ Library Feature
11.1.7. Debugging Your OpenCL Library Through Simulation (Preview) x
11.1.7.1. Compiling a Library for Simulation (-march=simulator) 11.1.7.2. Simulating Your OpenCL* Library 11.1.7.3. Troubleshooting Simulator Issues
11.2. Memory Attributes for Configuring Kernel Memory Systems x
11.2.1. Restrictions on the Use of Variable-specific Attributes
11.3. Kernel Attributes for Reducing the Overhead on Hardware Usage x
11.3.1. Hardware for Kernel Interface
11.3.1. Hardware for Kernel Interface x
11.3.1.1. Omit Hardware that Generates and Dispatches Kernel IDs 11.3.1.2. Omit Communication Hardware between the Host and the Kernel 11.3.1.3. Omit Hardware to Support the global_work_offset Argument in the clEnqueueNDRangeKernel API
11.4. Kernel Replication Using the num_compute_units(X,Y,Z) Attribute x
11.4.1. Customization of Replicated Kernels Using the get_compute_id() Function 11.4.2. Using Channels with Kernel Copies
A. Support Statuses of OpenCL Features x
A.1. Support Statuses of OpenCL 1.0 Features A.2. Support Statuses of OpenCL 1.2 Features A.3. Support Statuses of OpenCL 2.0 Features A.4. Intel® FPGA SDK for OpenCL™ Allocation Limits
A.1. Support Statuses of OpenCL 1.0 Features x
A.1.1. OpenCL 1.0 C Programming Language Implementation A.1.2. OpenCL C Programming Language Restrictions A.1.3. Argument Types for Built-in Geometric Functions A.1.4. Numerical Compliance Implementation A.1.5. Image Addressing and Filtering Implementation A.1.6. Atomic Functions A.1.7. Embedded Profile Implementation
A.2. Support Statuses of OpenCL 1.2 Features x
A.2.1. OpenCL 1.2 Runtime Implementation A.2.2. OpenCL 1.2 C Programming Language Implementation
A.3. Support Statuses of OpenCL 2.0 Features x
A.3.1. OpenCL 2.0 Headers A.3.2. OpenCL 2.0 Runtime Implementation A.3.3. OpenCL 2.0 C Programming Language Restrictions for Pipes
Product Discontinuance Notification
1. Intel® FPGA SDK for OpenCL™ Overview
2. Intel® FPGA SDK for OpenCL™ Offline Compiler Kernel Compilation Flows
3. Obtaining General Information on Software, Compiler, and Custom Platform
4. Managing an FPGA Board
5. Structuring Your OpenCL Kernel
6. Designing Your Host Application
7. Compiling Your OpenCL Kernel
8. Emulating and Debugging Your OpenCL Kernel
9. Developing OpenCL Applications Using Third-party IDEs
10. Developing OpenCL™ Applications Using Intel® Code Builder for OpenCL™
11. Intel® FPGA SDK for OpenCL™ Advanced Features
A. Support Statuses of OpenCL Features
B. Intel FPGA SDK for OpenCL Pro Edition Programming Guide Archives
C. Document Revision History of the Intel® FPGA SDK for OpenCL™ Pro Edition Programming Guide

C. Document Revision History of the Intel® FPGA SDK for OpenCL™ Pro Edition Programming Guide

Document Version Intel® Quartus® Prime Version Changes
2022.12.19 22.4
  • Maintenance release.
  • Added a warning about the -fast-compile flag leading to functional failures in Speeding Up Your OpenCL Compilation (-fast-compile).
2022.09.26 22.3
  • Maintenance release.
  • Changed the emulator environment variable OCL_TBB_NUM_WORKERS to CL_CONFIG_CPU_TBB_NUM_WORKERS in Emulator Environment Variables.
2022.06.21 22.2
  • Maintenance release.
2022.03.28 22.1
  • Maintenance release.
2021.12.13 21.4
  • Maintenance release.
2021.10.04 21.3
  • Changed all occurrences of "ModelSim - Intel FPGA Edition" to "Questa*- Intel FPGA Edition".
  • Changed all occurrences of Mentor Graphics to Siemens EDA*.
  • Changed all occurrences of "ModelSim - Intel FPGA Starter Edition" to "Questa*-Intel FPGA Starter Edition".
2021.06.23 21.2 Changed simple_dual_port_memory to simple_dual_port.
2021.06.21 21.2
  • Added back the offline compiler command option -ffp-reassoc that was removed in 21.1 release.
  • Renamed the offline compiler command option -ffp-reassoc to -ffp-reassociate.
2021.03.29 21.1
  • Made minor updates to the instructions in Debugging Your OpenCL Kernel on Linux.
  • Added a new topic Pipelining Loops in Non-task Kernels (-auto-pipeline) to describe the -auto-pipeline aoc command option.
  • Renamed the cluster-control attribute __attribute__((stall_enable)) as use_stall_enable_clusters. __attribute__((stall_enable)) is deprecated.
  • Made minor update to an important note in Specifying Number of SIMD Work-Items.
  • Made minor update to a restriction in Omit Communication Hardware between the Host and the Kernel.
  • Removed the flag -ffp-reassoc.
  • Updated the descriptions of the floating-point pragmas in Floating Point Optimizations (fp contract and fp reassociate Pragma).
2020.12.14 20.4
  • Made minor update in the description in Specifying the stall_enable Cluster-control Attribute.
  • Added a minor note about including the CL/cl_ext_intelfpga.h header file, in Partitioning Buffers Across Different Memory Types (Heterogeneous Memory).
2020.09.28 20.3
  • Removed -fpc and -fp-relaxed compilation flags because they are deprecated.
  • Updated the description of irreducible control flow feature in OpenCL C Programming Language Restrictions.
  • Added a note about -ffp-reassoc and -ffp-contract=fast flags exception in Creating an Object File From OpenCL Code.
  • Added information about -ghdl [<depth>] attribute in Compiling a Library for Simulation (-march=simulator).
  • Added a note about the placement of fp contract and fp reassoc pragma statements in Floating Point Optimizations (fp contract and fp reassoc Pragma).
  • Added a note about unrolling of nested loops with large bounds and an example about partial unroll in Unrolling a Loop (unroll Pragma).
  • Added a note about emulation performance expectations in the Emulating and Debugging Your OpenCL Kernel topic.
  • Removed the output in Displaying the Compilation Environment of an OpenCL Binary (env) topic since the output was no longer valid.
  • Renamed the topic title Collecting Profile Data During Kernel Execution to Triggering Collection of Profiling Data During Kernel Execution and made minor update to the topic description.
  • Renamed the topic title Profiling Enqueued and Autorun Kernels to Profiling Autorun Kernels and made minor update to the topic description.
  • Made minor update in Multistep Intel® FPGA SDK for OpenCL™ Pro Edition Design Flow.
  • Removed topics related to legacy emulator.
  • Minor description update in the Setting up the Emulator.
  • Minor update in the instructions and removed a note related to legacy emulator in the Debugging Your OpenCL Kernel on Linux.
  • Updated a note about the lack of support for Windows BSPs in Listing the Available FPGA Boards and Custom Platforms (-list-boards and -list-board-packages), Managing an FPGA Board, and Installing an FPGA Board.
2020.06.22 20.2
  • Minor update to Programming Strategies for Optimizing Pointer-to-Local Memory Size topic.
  • Added a new topic Specifying the stall_enable Cluster-control Attribute.
  • Updated the output sample of -list-board-packages and added a note in Listing the Available FPGA Boards and Custom Platforms (-list-boards and -list-board-packages) and Compiling a Kernel for a Specific FPGA Board and Custom Platform (-board=<board_name>) and (-board-package=<board_package_path>) topics.
  • Made minor updates with respect to BSP download instructions in Installing an FPGA Board.
  • Removed the mention of default FCD path in Uninstalling an FPGA Board.
  • Changed the BSP path in the following topics:
    • Querying the Device Name of Your FPGA Board (diagnose)
    • Emulating and Debugging Your OpenCL Kernel.
    • Using the Legacy Emulator
  • Updated the instruction to accessing the design example in Using an OpenCL Library that Works with Simple Functions (Example 1).
  • Modified texts to remove references to ap_int<d> and ap_uint<d> in Implementing Arbitrary Precision Integers.
  • Minor update to the description of pipe execution in a loop with multiple work items in Work-item Serial Execution of Pipes
2020.04.13 20.1
  • Updated the GCC versions in Setting up the Emulator, Emulating your OpenCL Kernel, and Limitations of the Intel® FPGA SDK for OpenCL™ Emulator.
  • Removed numreadports and numwriteports attributes from Memory Attributes for Configuring Kernel Memory Systems.
  • Changed all occurrences of "XML specification file" as "object manifest file".
  • Added a new topic Sharing Multiple Devices Across Multiple Host Programs.
  • Added more information about multiple command queues in Requirement for Multiple Command Queues to Execute Kernels Concurrently.
  • Added return values to the APIs and recommendations in API Functions for Interacting with cl_mem Pipe Objects Bound to Host-Accessible Pipe Kernel Arguments.
  • Added a note about synchronization in Direct Communication with Kernels via Host Pipes.
  • Changed a10gx_hostch to a10gx_hostpipe in Direct Communication with Kernels via Host Pipes.
  • Added examples and additional information about performing advanced compiler optimizations in Avalon Streaming Interface.
  • Added force_pow2_depth memory attribute to Memory Attributes for Configuring Kernel Memory Systems.
  • Changed the default work group size for kernels with barriers from 256 to 128 in OpenCL 1.0 C Programming Language Implementation and Specifying Work-Group Sizes.
  • Added a new topic Emulating Applications with a Channel That Reads or Writes to an I/O Channel.
  • Added a new topic Loop Fusion.
  • Added a new topic Fusing Adjacent Loops (loop_fuse Pragma).
  • Added a new topic Marking Loops to Prevent Automatic Fusion (nofusion Pragma).
  • Changed all instances of the memory attribute max_concurrency to private_copies.
  • Removed lines in the description of memory attribute private_copies that tells N is rounded up to the next power of two.
  • Added a warning about timing failure and possible solutions in RTL Reset and Clock Signals.
  • Updated a sentence about clock phase relationship in RTL Reset and Clock Signals.
  • Removed an entry about in-phase 2x clock in Restrictions and Limitations in RTL Support for the Intel® FPGA SDK for OpenCL™ Library Feature.
  • Changed -fmax=<fmax target in MHz> to -clock=<clock target in Hz/KHz/MHz/GHz or s/ms/us/ns/ps>.
  • Removed description about predefined preprocessor macro AOCL_BOARD_<board_name> from Using Predefined Preprocessor Macros in Conditional Compilation topic.
  • Removed a statement about fmax benefit from Forcing Ring Interconnect for Global Memory (-global-ring).
  • Removed Duplicating the Store Ring to Improve the Write Throughput to Global Memory (-duplicate-ring) topic.
  • Added a new topic Forcing a Single Store Ring to Reduce Area at the Expense of Write Throughput to Global Memory (-force-single-store-ring).
  • Added a new topic Forcing Fewer Read Data Reorder Units to Reduce Area at the Expense of Read Throughput to Global Memory (-num-reorder).
  • Reorganized and updated Ensuring Compatibility with Other OpenCL SDKs topic for clarity.
  • Removed the details about OpenCL data types in XML Elements for INTERFACE.
  • Added more information to Loop Interleaving Control (max_interleaving Pragma) topic.
2019.12.16 19.4
  • Updated Guideline for Naming the Kernel about using alphanumeric character, dash, underscore, or dot in file names.
  • Added a subsection about compatibility with ModelSim - Intel FPGA Starter Edition software in the Limitations of the Simulator topic.
  • Updated a limitation about debugger in Restrictions and Limitations in RTL Support for the Intel® FPGA SDK for OpenCL™ Library Feature.
  • Added a note about BSP support in Direct Communication with Kernels via Host Pipes.
  • Removed buffer_location example above table Additional XML Elements to Support External Memory Access as well as description in the named table.
  • Added a note about how to disable debugging and enable optimizations in Emulating Your OpenCL Kernel.
  • Added a note about some source lines going out of order in Debugging Your OpenCL Kernel on Linux.
  • Updated information about the resetn signal in XML Syntax of an RTL Module.
  • Updated the description of the .aoco file with a mention of -save-temps option in Kernel Compilation Flows.
  • Removed .aoco file in One-step Compilation for Simple Kernels.
  • Minor update in Multistep Intel® FPGA SDK for OpenCL™ Pro Edition Design Flow.
  • Added a statement about -save-temps in Compiling and Linking Your Kernels or Object Files without Building Hardware (-rtl).
  • Included the option -save-temps in Specifying the Name of an Intel® FPGA SDK for OpenCL™ Offline Compiler Output File (-o <filename>) and Compiling a Kernel for a Specific FPGA Board and Custom Platform (-board=<board_name>) and (-board-package=<board_package_path>).
  • Changed cl_ext.h to cl_ext_intelfpga.h in Accessing Custom Platform-Specific Functions.
2019.10.30 19.3 Removed the pragma directive #pragma OPENCL EXTENSION cl_intel_arbitrary_precision_integers : enable and details about declaring the arbitrary precision integers in the Implementing Arbitrary Precision Integers topic.
2019.09.30 19.3
  • Removed the topic Debugging Your OpenCL System That is Gradually Slowing Down since runtime performance no longer degrades due to event mismanagement.
  • Added a new topic Enabling All Global Memory.
  • Made a minor update in the description by removing some texts in the Forcing Ring Interconnect for Global Memory (-global-ring) topic.
  • Updated Out-of-Order Command Queues topic to describe the support for out-of-order command queues in this release.
  • Updated Requirement for Multiple Command Queues to Execute Kernels Concurrently with more information.
  • In Memory Attributes for Configuring Kernel Memory Systems topic, made the following updates:
    • Deprecated numreadports and numwriteports attributes.
    • Added max_replicates(N) and simple_dual_port_memory attributes.
    • Updated descriptions of the remaining attributes.
  • Removed some of the restrictions since they no longer were a restriction in the Restrictions on the Use of Variable-specific Attributes topic.
  • Added another limitation about OpenCL kernels calling HLS tasks in the Limitations of the Incremental Compilation Feature topic.
  • Added Loop Interleaving Control (max_interleaving Pragma).
  • Added a subsection about simulator backward compatibility in the Limitations of the Simulator.
  • Added a note about GCC 6.3.0 and made some minor updates in the Emulating your OpenCL Kernel topic.
  • Added information about the library creation tools in the following topics:
    • OpenCL Library
    • Creating Library Objects From OpenCL Code
    • Creating an Object File from OpenCL Code
    • Packaging Multiple Object Files into a Library File
  • Added Relaxing the Order of Floating-Point Operations (-ffp-reassoc) to describe the new aoc command option.
  • Added Reducing Floating-Point Rounding Operations (-ffp-contract) to describe the new aoc command option.
  • Added Floating Point Optimizations (fp contract and fp reassoc Pragma) to describe the new pragmas.
  • Added a note in Relaxing the Order of Floating-Point Operations (-fp-relaxed) and Reducing Floating-Point Rounding Operations (-fpc) about their deprecation in a future release.
  • Updated the limits for some of the items in the Allocation Limits topic.
  • Changed -fp-relaxed to -ffp-reassoc in the Programming Strategies for Inferring the Accumulator topic.
  • Changed -fp-relaxed to -ffp-reassoc in the Discrepancies in Hardware and Emulator Results topic.
  • Updated a code snippet In Using OpenCL ICD Extension APIs.
  • Changed two instances of "emulator" as "legacy emulator" in Simulating Your OpenCL* Library.
  • Changed march=emulator to -march=emulator -legacy-emulator in Compiling a Kernel for Emulation (Legacy Emulator) (-march=emulator -legacy-emulator) .
  • Made minor updates in Using the Legacy Emulator.
  • Changed the topic title from Fast Emulator Environment Variables to Emulator Environment Variables. Also added CL_CONFIG_CPU_EMULATE_DEVICES variable description in the topic.
  • Changed the topic title from Extensions Supported by the Fast Emulator to Extensions Supported by the Emulator. Also changed references to fast emulator as emulator within the topic.
  • Changed the topic title from Fast Emulator Known Issues to Emulator Known Issues. Also changed references to fast emulator as emulator within the topic.
  • Removed unrecognized attribute warning for uses_global_work_offset kernel attribute in the Emulator Known Issues topic.
  • Added another limitation about GCC version in the Limitations of the Emulator topic.
  • Made the following changes in the Compiling a Kernel for Emulation (-march=emulator) topic:
    • Changed -march=emulator -fast-emulator to march=emulator.
    • Removed a bullet point about QUARTUS_ROOTDIR_OVERRIDE variable.
    • Updated the code snippet.
  • Made the following updates in the Setting up the Emulator topic:
    • Changed the title from Setting up the Fast Emulator to Setting up the Emulator.
    • Removed manual installation of the Intel® FPGA SDK for OpenCL™ .
    • Changed fast emulator references as emulator within the topic.
    • Added a note about emulator requiring GCC6.3.0 or later.
2019.07.01 19.2
2019.04.22 19.1 Fixed broken links.
2019.04.01 19.1
2018.12.24 18.1.1
2018.09.27 18.1
2018.09.24 18.1
2018.08.03 18.0
2018.06.14 18.0
2018.05.23 18.0
2018.05.04 18.0
Date Version Changes
December 2017 2017.12.08
November 2017 2017.11.06
  • Moved topics into separate chapters.
  • Rebranded references to the following:
    • The macro ALTERA_CL to INTELFPGA_CL.
    • The environment variable ALTERAOCLSDKROOT to INTELFPGAOCLSDKROOT.
    • The environment variable CL_CONTEXT_PROGRAM_VARIABLES_TOTAL_SIZE_ALTERA to CL_CONTEXT_PROGRAM_VARIABLES_TOTAL_SIZE_INTELFPGA
    • clGetExtensionFunctionAddress to clGetExtensionFunctionAddressIntelFPGA
    • The environment variable CL_CONTEXT_EMULATOR_DEVICE_ALTERA to CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA
    • write_channel_altera to write_channel_intel
    • write_channel_nb_altera to write_channel_nb_intel
    • CL_MEM_BANK to CL_CHANNEL
    • CL_MEM_BANK_1_INTEL to CL_CHANNEL_1_INTELFPGA
    • CL_MEM_BANK_2_INTEL to CL_CHANNEL_2_INTELFPGA
    • Arria 10 to Intel® Arria® 10
    • Quartus Prime to Intel Quartus Prime
    • Intel® FPGA SDK for OpenCL™ Profiler to Intel FPGA Dynamic Profiler for OpenCL
    • TimeQuest Timing Analyzer to Timing Analyzer
    • Qsys Pro to Platform Designer
  • In Intel FPGA SDK for OpenCL FPGA Programming Flow, added FPGA data flow architecture diagram and related text.
May 2017 2017.05.08
October 2016 2016.10.31
  • Rebranded the Altera SDK for OpenCL to Intel® FPGA SDK for OpenCL™ .
  • Rebranded the Altera Offline Compiler to Intel® FPGA SDK for OpenCL™ Offline Compiler.
  • Deprecated and removed support for big-endian system, resulting in the following documentation changes:
    • Removed the topic Compiling a Kernel for a Big-Endian System (--big-endian).
    • Removed big-endian (64-bit) from the list of architectures that the host application can target.
  • Added the topic Displaying the Compilation Environment of an OpenCL Binary to introduce the aoc env command.
  • Removed Adding Source References to Optimization Reports (-g) because the offline compiler automatically includes source information in the compiler reports and enables symbolic debug during emulation on an x86 Linux machine.
  • Added the topic Removing Debug Data from Compiler Reports and Source Code from the .aocx File (-g0) to introduce the -g0 aoc command option.
  • In Limitations of the Intel® FPGA SDK for OpenCL™ Emulator, removed the limitation "The Emulator does not support half data type".
  • In Linking Your Host Application to the Khronos ICD Loader Library, provided an update that the Intel® -supplied ICD Loader Library supports OpenCL Specification version 1.0 as well as implemented APIs from the OpenCL Specification versions 1.1, 1.2, and 2.0.
  • In Managing an FPGA Board, provided the following updates:
    • Noted that the SDK supports installation of multiple Custom Platforms. To use the SDK utilities on each board in a multi-board installation, the AOCL_BOARD_PACKAGE_ROOT environment variable setting must correspond to the Custom Platform subdirectory of the associated board.
    • Noted that in a system with multiple Custom Platforms, the host program should use ACD to discover the boards instead of directly linking to the MMD libraries.
  • Added the topic Reviewing Your Kernel's report.html File and included deprecation notice for the analyze-area utility option. As a result of introducing the HTML report, removed the following topics:
    • Reviewing Your Kernel's Resource Usage Information in the Area Report
    • Accessing the Area Report
    • Layout of the Area Report
  • In Multistep Design Flow, updated the design steps and the figure The Multistep Intel® FPGA SDK for OpenCL™ Design Flow to replace area report with the HTML report, and remove information on enabling -g.
  • In Inferring a Register, corrected the text following the code snippet that explained how the offline compiler decide on the implementation of the array in hardware.
  • In Linking to the ICD Loader Library on Windows, updated the text to improve clarity.
  • In Support Statuses of OpenCL Features section, made the following updates:
    • Rebranded the Altera SDK for OpenCL to Intel® FPGA SDK for OpenCL™ .
    • Rebranded the Altera Offline Compiler to Intel® FPGA SDK for OpenCL™ Offline Compiler.
    • Modified information in the Intel® FPGA SDK for OpenCL™ Allocation Limits section:
      • Updated information regarding minimum global memory allocation by runtime.
      • Updated the maximum number of queues from 70 to 256.
      • Updated the maximum number of kernels per FPGA device from 64 to no static limit when compiling to hardware and 256 when compiling to emulator.
    • In OpenCL 1.0 C Programming Language Implementation, under the Description column for half-precision float, added a note that this feature is supported in the Emulator. In addition, updated the support status of half-precision float from X to ○.
    • Under Support Statuses of OpenCL 2.0 Features, added the topic OpenCL 2.0 Headers to explain that using the OpenCL 2.0 headers to call unsupported APIs results in an error.
May 2016 2016.05.02
  • Added a schematic diagram of the AOCL programming model in the Altera SDK for OpenCL FPGA Programming Flow section.
  • Moved the figure The AOCL FPGA Programming Flow to the Altera Offline Compiler Kernel Compilation Flows section.
  • Updated the figure The Multistep AOCL Design Flow and associated text to include the Review Area Report step.
  • Added information on the single-cycle floating-point accumulator feature for single work-item kernels. Refer to the Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels section for more information.
  • Added information in the Emulating Your OpenCL Kernel section on multi-device support for emulation alongside other OpenCL SDKs using ICD.
  • Included information on the enhanced area report feature:
    • Added the option to invoke the analyze-area AOCL utility command to generate an HTML area report.
    • Included a topic that describes the layout of the HTML area report.
  • In Linking to the ICD Loader Library on Windows, removed $(AOCL_LDLIBS) from the code example for the modified Makefile.
  • In the Multiple Work-Item Ordering sections for channels and pipes, modified the characteristics that the AOCL uses to check whether the channel or pipe call is work-item invariant.
  • Added Intel FPGA SDK for OpenCL Advanced Feature section.
  • In OpenCL 1.2 Runtime Implementation under Support Statuses of OpenCL Features sections, noted that AOCL supports the clSetEventCallback, clGetKernelArgInfo, and clSetMemObjectDestructorCallback APIs.
November 2015 2015.11.02
  • Added the option to invoke the aoc command with no argument to access the Altera Offline Compiler help menu.
  • Updated the Multiple Host Threads section to specify that the OpenCL™ host runtime is thread-safe.
  • Updated the following figure and sections to reflect multiple kernel source file support:
    • The figure The AOCL FPGA Programming Flow in the AOCL FPGA Programming Flow section
    • The Compiling Your Kernel to Create Hardware Configuration File section
    • The Compiling Your Kernel without Building Hardware (-c) section
  • In Multiple Work-Item Ordering for Channels, removed misleading text.
  • Updated the Overview of Channels Implementation figure.
  • Updated the following sections on OpenCL pipes:
    • Overview of a Pipe Network Implementation figure in Overview of the OpenCL Pipe Functions
    • Emulation support in Restrictions in OpenCL Pipes Implementation section
    • Replaced erroneous code with the correct syntax
    • Added link to Implementing I/O Pipes Using the io Attribute in Declaring the Pipe Handle
  • Added a reminder in Programming an FPGA via the Host that you should release an event object after use to prevent excessive memory usage.
  • In Support Statuses of OpenCL Features section, made the following updates:
    • Categorized feature support statuses and limitations based on OpenCL Specification versions.
    • Added the following functions to the list of OpenCL-conformant double precision floating-point functions:

      sinh / cosh / tanh / asinh / acosh / atanh / pow / pown / powr / tanh / atan / atan2 / ldexp / log1p / sincos

    • In OpenCL 1.2 Runtime Implementation, added sub-buffer object support.
    • In OpenCL 2.0 Runtime Implementation, added preliminary shared virtual memory support.
    • In Altera SDK for OpenCL Allocation Limits, added a minimum global memory allocation limit by the runtime.
May 2015 15.0.0
  • In Guidelines for Naming the Kernel, added entry that advised against naming an OpenCL kernel kernel.cl.
  • In Instrumenting the Kernel Pipeline with Performance Counters (--profile), specified that you should run the host application from a local disk to avoid potential delays caused by slow network disk accesses.
  • In Emulating and Debugging Your OpenCL Kernel, modified Caution note to indicate that you must emulate a design targeting an SoC on a non-SoC board.
  • In Emulating Your OpenCL Kernel, updated command to run the host application and added instruction for overriding default temporary directory containing <process_ID>-libkernel.so.
  • Introduced the --high-effort aoc command flag in Resolving Hardware Generation Fitting Errors during Kernel Compilation.
  • In Enabling Double Precision Floating-Point Operations, introduced the OPENCL EXTENSION pragma for enabling double precision floating-point operations.
  • Introduced OpenCL pipes support. Refer to Implementing OpenCL Pipes (and subsequent subtopics) and Creating a Pipe Object in Your Host Application for more information.
  • In AOCL Channels Extension: Restrictions, added code examples to demonstrate how to statically index into arrays of channel IDs.
  • In Multiple Host Threads, added recommendation for synchronizing OpenCL host function calls in a multi-threaded host application.
  • Introduced ICD and ACD support. Refer to Linking Your Host Application to the Khronos ICD Loader Library for more information.
  • Introduced clGetBoardExtensionFunctionAddressAltera for referencing user-accessible functions. Refer to Accessing Custom Platform-Specific Functions for more information.
  • In Support Statuses of OpenCL Features section, made the following updates:
    • Listed the double precision floating-point functions that the Altera® SDK for OpenCL™ supports preliminarily.
    • Added OpenCL C Programming Language Restrictions for Pipes.
December 2014 14.1.0
  • Reorganized information flow. Information is now presented based on the tasks you might perform using the Altera® SDK for OpenCL™ (AOCL) or the Altera RTE for OpenCL.
  • Removed information pertaining to the --util <N> and -O3 Altera Offline Compiler (AOC) options.
  • Added the following information on PLDA QuickUDP IP core licensing in Compiling Your OpenCL Kernel:
    1. A PLDA QuickUDP IP core license is required for the Stratix® V Network Reference Platform or a Custom Platform that uses the QuickUDP IP core.
    2. Improper installation of the QuickUDP IP core license causes compilation to fail with an error message that refers to the QuickTCP IP core.
  • Added reminder that conditionally shifting a large shift register is not recommended.
  • Removed the Emulating Systems with Multiple Devices section. A new env CL_CONTEXT_EMULATOR_DEVICE_ALTERA=<number_of_devices> command is now available for emulating multiple devices.
  • Removed language support limitation from the Limitations of the AOCL Emulator section.
  • In AOCL Allocation Limits under Support Statuses of OpenCL Features section, updated the maximum number of kernels per FPGA device from 32 to 64.
June 2014 14.0.0
  • Removed the --estimate-throughput and --sw-dimm-partition AOC options
  • Added the -march=emulator, -g, --big-endian, and --profile AOC options
  • --no-interleaving needs <global_memory_type> argument
  • -fp-relaxed=true is now --fp-relaxed
  • -fpc=true is now --fpc
  • For non-SoC devices, aocl diagnostic is now aocl diagnose and aocl diagnose <device_name>
  • program and flash need <device_name> arguments
  • Added Identifying the Device Name of Your FPGA Board
  • Added AOCL Profiler Utility
  • Added AOCL Channels Extension and associated subsections
  • Added Attributes for Channels
  • Added Match Data Layouts of Host and Kernel Structure Data Types
  • Added Register Inference and Shift Register Inference
  • Added Channels and Multiple Command Queues
  • Added Shared Memory Accesses for OpenCL Kernels Running on SoCs
  • Added Collecting Profile Data During Kernel Execution
  • Added Emulate and Debug Your OpenCL Kernel and associated subsections
  • Updated AOC Kernel Compilation Flows
  • Updated -v
  • Updated Host Binary Requirement
  • Combined Partitioning Global Memory Accesses and Partitioning Heterogeneous Global Memory Accesses into the section Partitioning Global Memory Accesses
  • Updated AOC Allocation Limits in Appendix A
  • Removed max_unroll_loops, max_share_resources, num_share_resources, and task kernel attributes
  • Added packed, and aligned(<N>) kernel attributes
  • In Support Statuses of OpenCL Features section, updated the following AOCL allocation limits:
    • Maximum number of contexts
    • Maximum number of queues
    • Maximum number of event objects per context
December 2013 13.1.1
  • Removed the section -W and -Werror, and replaced it with two sections: -W and -Werror.
  • Updated the following contents to reflect multiple devices support:
    • The figure The AOCL FPGA Programming Flow.
    • --list-boards section.
    • -board <board_name> section.
    • Added the subsection Programming Multiple FPGA Devices under FPGA Programming.
  • The following contents were added to reflect heterogeneous global memory support:
    • --no-interleaving section.
    • buffer_location kernel attribute under Kernel Pragmas and Attributes.
    • Partitioning Heterogeneous Global Memory Accesses section.
  • Modified support status designations in Appendix: Support Statuses of OpenCL Features.
  • Removed information on OpenCL programming language restrictions from the section OpenCL Programming Language Implementation, and presented the information in a new section titled OpenCL Programming Language Restrictions.
November 2013 13.1.0
  • Reorganized information flow.
  • Updated and renamed Intel® FPGA SDK for OpenCL™ Compilation Flow to AOCL FPGA Programming Flow.
  • Added figures One-Step AOC Compilation Flow and Two-Step AOC Compilation Flow.
  • Updated the section Contents of the AOCL Version 13.1.
  • Removed the following sections:
    • OpenCL Kernel Source File Compilation.
    • Using the Altera Offline Kernel Compiler.
    • Setting Up Your FPGA Board.
    • Targeting a Specific FPGA Board.
    • Running Your OpenCL Application.
    • Consolidating Your Kernel Source Files.
    • Aligned Memory Allocation.
    • Programming the FPGA Hardware.
    • Programming the Flash Memory of an FPGA.
  • Updated and renamed Compiling the OpenCL Kernel Source File to AOC Compilation Flows.
  • Renamed Passing File Scope Structures to OpenCL Kernels to Use Structure Arguments in OpenCL Kernels.
  • Updated and renamed Augmenting Your OpenCL Kernel by Specifying Kernel Attributes and Pragmas to Kernel Pragmas and Attributes.
  • Renamed Loading Kernels onto an FPGA to FPGA Programming.
  • Consolidated Compiling and Linking Your Host Program, Host Program Compilation Settings, and Library Paths and Links into a single section.
  • Inserted the section Preprocessor Macros.
  • Renamed Optimizing Global Memory Accesses to Partitioning Global Memory Accesses.
June 2013 13.0 SP1.0
  • Added the section Setting Up Your FPGA Board.
  • Removed the subsection Specifying a Target FPGA Board under Kernel Programming Considerations.
  • Inserted the subsections Targeting a Specific FPGA Board and Generating Compilation Reports under Compiling the OpenCL Kernel Source File.
  • Renamed File Scope __constant Address Space Qualifier to __constant Address Space Qualifiers, and inserted the following subsections:
    • Function Scope __constant Variables.
    • File Scope __constant Variables.
    • Points to __constant Parameters from the Host.
  • Inserted the subsection Passing File Scope Structures to OpenCL Kernels under Kernel Programming Considerations.
  • Renamed Modifying Your OpenCL Kernel by Specifying Kernel Attributes and Pragmas to Augmenting Your OpenCL Kernel by Specifying Kernel Attributes and Pragmas.
  • Updated content for the unroll pragma directive in the section Augmenting Your OpenCL Kernel by Specifying Kernel Attributes and Pragmas.
  • Inserted the subsections Out-of-Order Command Queues and Modifying Host Program for Structure Parameter Conversion under Host Programming Considerations.
  • Updated the sections Loading Kernels onto an FPGA Using clCreateProgramWithBinary and Aligned Memory Allocation.
  • Updated flash programming instructions.
  • Renamed Optional Extensions in Appendix B to Atomic Functions, and updated its content.
  • Removed Platform Layer and Runtime Implementation from Appendix B.
May 2013 13.0.1
  • Explicit memory fence functions are now supported; the entry is removed from the table OpenCL Programming Language Implementation.
  • Updated the section Programming the Flash Memory of an FPGA.
  • Added the section Modifying Your OpenCL Kernel by Specifying Kernel Attributes and Pragmas to introduce kernel attributes and pragmas that can be implemented to optimize kernel performance.
  • Added the section Optimizing Global Memory Accesses to discuss data partitioning.
  • Removed the section Programming the FPGA with the aocl program Command from Appendix A.
May 2013 13.0.0
  • Updated compilation flow.
  • Updated kernel compiler commands.
  • Included Altera® OpenCL™ Utility commands. SDK for
  • Added the section OpenCL Programming Considerations.
  • Updated flash programming procedure and moved it to Appendix A.
  • Included a new clCreateProgramWithBinary SDK for FPGA hardware programming flow.
  • Moved the hostless clCreateProgramWithBinary hardware programming flow to Appendix A under the title Programming the FPGA with the aocl program Command.
  • Moved updated information on allocation limits and OpenCL language support to Appendix B.
November 2012 12.1.0 Initial release.
Level Two Title

Did you find the information on this page useful?

Characters remaining:

Feedback Message