1.5. ALTERA_CORDIC IP Core Signals
Name  Type  Description 

clk  Input  Clock. 
en  Input  Enable. Only available when you turn on Generate an enable port. 
areset  Input  Reset. 
Name  Type  Configuration  Range  Description 

a  Input  Signed input  [− π,+π]  Specifies the number of fractional bits (F _{ IN }). The total width of this input is F _{IN}+3.Two extra bits are for the range (representing π) and one bit for the sign. Provide the input in two’s complement form. 
Unsigned input  [0,+π /2]  Specifies the number of fractional bits (F _{IN}). The total width of this input is w _{IN}=F _{IN}+1. The one extra bit accounts for the range (required to represent π/2).  
s, c  Output  Signed input  [−1,1]  Computes sin(a) and cos(a) on a userspecified output fraction width(F). The output has width w _{OUT}= F _{OUT}+2 and is signed. 
Unsigned input  [0,1]  Computes sin(a) and cos(a) on a userspecified output fraction width(F _{OUT}). The output has the width w _{OUT}= F _{OUT}+1 and is unsigned. 
Name  Type  Configuration  Range  Details 

x, y  Input  Signed input  Given by w, F  Specifies the total width (w) and number fractional bits (F) of the input. Provide the inputs in two’s complement form. 
Unsigned input  Specifies the total width (w) and number fractional bits (F) of the input.  
a  Ouput  Signed input  [− π,+π]  Computes atan2(y,x) on a userspecified output fraction width (F). The output has the width w _{OUT}= F _{OUT}+2 and is signed. 
Unsigned input  [0,+π /2]  Computes atan2(y,x) on output fraction width (F _{OUT}). The output format has the width w _{OUT} = F _{OUT}+2 and is signed. However, the output value is unsigned. 
Name  Direction  Configuration  Range  Details 

x, y  Input  Signed input  Given by w, F  Specifies the total width (w) and number fractional bits (F) of the input. Provide the inputs in two’s complement form. 
q  Output  [− π,+π]  Computes atan2(y,x) on a userspecified output fraction width F _{ q }. The output has the width w _{ q }=F _{ q }+3 and is signed. 

r  Given by w, F  Computes K (x ^{2}+y ^{2})^{0.5}. The total width of the output is w _{ r }=F _{ q }+3, or w _{ r }=F _{ q }+2 with scale factor compensation. The number of meaningful bits depends on the number of iterations which depends on F _{ q }. The format of the output depends on the input format. MSB(M _{OUT})=MSB_{IN}+2, or MSB(M _{OUT})=MSB_{IN}+1 with scale factor compensation 

x, y  Input  Unsigned input  Given by w,F  Specifies the total width (w) and number fractional bits (F) of the input. 
q  Output  [0,+π /2]  Computes atan2(y,x) on an output fraction width F _{ q }. The output has the width w _{ q }=F _{ q }+2 and is signed. 

r  Given by w,F  Computes K( x ^{2}+y ^{2})^{0.5}. The total width of the output is w _{ r }=F _{ q }+3, or w _{ r }=F _{ q }+2 with scale factor compensation. MSB(M _{OUT})=MSB_{IN}+2, or MSB(M _{OUT})=MSB_{IN}+1 with scale factor compensation. 
Name  Direction  Configuration  Range  Details 

x, y  Input  Signed input  [−1,1]  Specifies the fraction width (F), total number of bits is w = F+2. Provide the inputs in two’s complement form. 
Unsigned input  [0,1]  Specifies the fraction width (F), total number of bits is w = F+1.  
a  Input  Signed input  [− π,+π]  Number of fractional bits is F (provided previously for x and y), total width is w _{a} = F+3. 
Unsigned input  [0,+π]  Number of fractional bits is F (provided previously for x and y), total width is w _{a} = F+2.  
x0, y0  Output  Signed input  [−2^{0.5} ,+2^{0.5}]K  Number of fractional bits F _{OUT}, where w _{OUT} = F_{OUT} +3 or w _{OUT} = F_{OUT} +2 with scale factor reduction. 
Unsigned input 
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