ALTERA_CORDIC IP Core User Guide

ID 683808
Date 5/08/2017
Public

1.5. ALTERA_CORDIC IP Core Signals

Table 6.  Common Signals
Name Type Description
clk Input Clock.
en Input Enable. Only available when you turn on Generate an enable port.
areset Input Reset.
Table 7.  Sin Cos Function Signals
Name Type Configuration Range Description
a Input Signed input [ π,+π] Specifies the number of fractional bits (F IN ). The total width of this input is F IN+3.Two extra bits are for the range (representing π) and one bit for the sign. Provide the input in two’s complement form.
Unsigned input [0,+π /2] Specifies the number of fractional bits (F IN). The total width of this input is w IN=F IN+1. The one extra bit accounts for the range (required to represent π/2).
s, c Output Signed input [1,1] Computes sin(a) and cos(a) on a user-specified output fraction width(F). The output has width w OUT= F OUT+2 and is signed.
Unsigned input [0,1] Computes sin(a) and cos(a) on a user-specified output fraction width(F OUT). The output has the width w OUT= F OUT+1 and is unsigned.
Table 8.  Atan2 Function Signals
Name Type Configuration Range Details
x, y Input Signed input Given by w, F Specifies the total width (w) and number fractional bits (F) of the input. Provide the inputs in two’s complement form.
Unsigned input Specifies the total width (w) and number fractional bits (F) of the input.
a Ouput Signed input [ π,+π] Computes atan2(y,x) on a user-specified output fraction width (F). The output has the width w OUT= F OUT+2 and is signed.
Unsigned input [0,+π /2] Computes atan2(y,x) on output fraction width (F OUT). The output format has the width w OUT = F OUT+2 and is signed. However, the output value is unsigned.
Table 9.  Vector Translate Functions Signals
Name Direction Configuration Range Details
x, y Input Signed input Given by w, F Specifies the total width (w) and number fractional bits (F) of the input. Provide the inputs in two’s complement form.
q Output [ π,+π]

Computes atan2(y,x) on a user-specified output fraction width F q . The output has the width w q =F q +3 and is signed.

r Given by w, F

Computes K (x 2+y 2)0.5.

The total width of the output is w r =F q +3, or w r =F q +2 with scale factor compensation.

The number of meaningful bits depends on the number of iterations which depends on F q . The format of the output depends on the input format.

MSB(M OUT)=MSBIN+2, or MSB(M OUT)=MSBIN+1 with scale factor compensation

x, y Input Unsigned input Given by w,F Specifies the total width (w) and number fractional bits (F) of the input.
q Output [0,+π /2]

Computes atan2(y,x) on an output fraction width F q . The output has the width w q =F q +2 and is signed.

r Given by w,F Computes K( x 2+y 2)0.5.

The total width of the output is w r =F q +3, or w r =F q +2 with scale factor compensation.

MSB(M OUT)=MSBIN+2, or MSB(M OUT)=MSBIN+1 with scale factor compensation.

Table 10.  Vector Rotate Function Signals
Name Direction Configuration Range Details
x, y Input Signed input [1,1] Specifies the fraction width (F), total number of bits is w = F+2. Provide the inputs in two’s complement form.
Unsigned input [0,1] Specifies the fraction width (F), total number of bits is w = F+1.
a Input Signed input [ π,+π] Number of fractional bits is F (provided previously for x and y), total width is w a = F+3.
Unsigned input [0,+π] Number of fractional bits is F (provided previously for x and y), total width is w a = F+2.
x0, y0 Output Signed input [20.5 ,+20.5]K Number of fractional bits F OUT, where w OUT = FOUT +3 or w OUT = FOUT +2 with scale factor reduction.
Unsigned input

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