F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

Download PDF
ID 683804
Date 7/09/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

3.5. Registers

The PTP monitor registers are part of the Packet Client block of each Ethernet IP instance. The Packet Client base address for each IP instance is available in Register Maps.
For example, the PTP monitor registers address in the third Ethernet IP instance is equivalent to 0x0210_0400, where:
  • 0x0200_0000 is the Ethernet IP: Instance 2 base address
  • 0x0010_0000 is the Packet Client base address for the specified IP instance
  • 4*0x100 is the PTP monitor base address for the specified IP instance
Table 12.  PTP Monitor RegistersAll address offsets are specified in the word address format.
Word Address Name Bit Offset Default Value Access Description
0x100 Soft Reset 0 1'b0 RW Soft reset for PTP monitor.

Prior to every burst iteration, you must write 1'b1 followed by 1'b0.
0x101 TX_PKT_VALID 0 1'b0 RO
Indicates the TX packet data is available.
  • 0: No packet content is available for read out.
  • 1: Packet content is available.
TX_PTP_ETS_VALID 1 1'b0 RO
Indicates the TX egress timestamp is available.
  • 0: No timestamp is available for read out.
  • 1: Timestamp is available.
RX_PKT_VALID 2 1'b0 RO
Indicates the RX packet data is available.
  • 0: No packet content is available for read out.
  • 1: Packet content is available.
0x102 TX_PKT_DATA_63_32 [31:0] 32'h0 RO Indicates the TX packet data for 64-bit segment.
0x103 TX_PKT_DATA_31_0 [31:0] 32'h0 RO
0x104 TX_PKT_INFRAME 0 1'b0 RO Specifies TX packet inframe.
TX_PKT_SOP 1 1'b0 RO Indicates the start-of-packet (SOP) for TX packet.
TX_PKT_EOP 2 1'b0 RO Indicates the end-of-packet (EOP) for TX packet.
TX_PKT_EMPTY [5:3] 3'b000 RO Indicates that TX packet is empty.
TX_PKT_ERROR 6 1'b0 RO Indicates a TX packet error.
TX_PKT_SKIP_CRC 7 1'b0 RO Indicates the setting of skip_crc signal for TX packet.
0x105 TX_PTP_TS_REQ 0 1'b0 RO Indicates a received request for TX PTP timestamp.
TX_PTP_INS_ETS 1 1'b0 RO Indicates TX PTP insert egress timestamp.
TX_PTP_INS_CF 2 1'b0 RO Indicates that TX PTP updated the Correction Field with residence time.
TX_PTP_ZERO_CSUM 3 1'b0 RO TX PTP clear checksum field for IPv4 packet.
TX_PTP_UPDATE_EB 4 1'b0 RO Indicates that TX PTP updated extended bytes for IPv6 packets.
TX_PTP_P2P 5 1'b0 RO Indicates that TX PTP inserted peer-to-peer value for MeanPathDelay signal.
TX_PTP_ASYM 6 1'b0 RO Indicates that TX PTP inserted asymmetry delay.
Reserved
TX_PTP_ASYM_SIGN 8 1'b0 RO Indicates the asymmetry delay sign bit for TX PTP packets.
TX_PTP_ASYM_PTP_IDX [15:9] 7'h0 RO TX PTP index from asymmetry and peer-to-peer lookup table.
TX_PTP_TS_OFFSET [31:16] 16'h0 RO Indicates the TX PTP timestamp offset.
0x106 TX_PTP_CF_OFFSET [15:0] 16'h0 RO Indicates offset for the TX PTP CorrectionField signal.
TX_PTP_CSUM_OFFSET [31:16] 16'h0 RO Indicates offset for the TX PTP ChecksumField signal.
0x107 TX_PTP_USR_FP [31:0] 32'h0 RO Specifies your TX PTP fingerprint. The valid range depends on the PTP_FP_WIDTH setting in the IP Parameter Editor.
0x108 TX_PTP_ITS_95_64 [31:0] 32'h0 RO Specifies the 96-bit TX PTP ingress timestamp.
0x109 TX_PTP_ITS_63_32 [31:0] 32'h0 RO
0x10A TX_PTP_ITS_31_0 [31:0] 32'h0 RO
0x10C TX_PTP_ETS_FP [31:0] 32'h0 RO Specifies TX PTP fingerprint. The valid range depends on the PTP_FP_WIDTH setting in the IP Parameter Editor.
0x10D TX_PTP_ETS_95_64 [31:0] 32'h0 RO Specifies the 96-bit TX PTP egress timestamp.
0x10E TX_PTP_ETS_63_32 [31:0] 32'h0 RO
0x10F TX_PTP_ETS_31_0 [31:0] 32'h0 RO
0x110 RX_PKT_INFRAME 0 1'b0 RO Specifies RX packet inframe.
RX_PKT_SOP 1 1'b0 RO Indicates the start-of-packet (SOP) for the RX packet.
RX_PKT_EOP 2 1'b0 RO Indicates the end-of-packet (EOP) for the RX packet.
RX_PKT_EMPTY [5:3] 3'b000 RO Indicates that RX packet is empty.
RX_PKT_ERROR [11:6]   RO Indicates a RX packet error.
RX_PKT_FCS_ERROR 12 1'b0 RO Indicates a RX packet FCS error.
0x111 RX_PKT_DATA_63_32 [31:0] 32'h0 RO Specifies the 64-bit segment for RX packet data.
0x112 RX_PKT_DATA_31_0 [31:0] 32'h0 RO
0x114 RX_PTP_ITS_95_64 [31:0] 32'h0 RO

Specifies the 96-bit RX PTP ingress timestamp.
0x115 RX_PTP_ITS_63_32 [31:0] 32'h0 RO
0x116 RX_PTP_ITS_31_0 [31:0] 32'h0 RO
Related Information
Level Two Title