1.4. Clock Control Intel Stratix 10 FPGA IP v18.0
| Description | Impact |
|---|---|
| Renamed Stratix 10 Clock Control IP core to Clock Control Intel Stratix 10 FPGA IP core as per Altera rebranding. | — |
| Renamed ‘falling edge’ mode to ‘negative latch’ mode. | — |
| Description | Impact |
|---|---|
| Renamed Stratix 10 Clock Control IP core to Clock Control Intel Stratix 10 FPGA IP core as per Altera rebranding. | — |
| Renamed ‘falling edge’ mode to ‘negative latch’ mode. | — |