6.1.1. Sink Word Alignment and Channel Deskew

HDMI Intel® FPGA IP User Guide

Download PDF

ID 683798

Date 6/26/2023

Version

Public

A newer version of this document is available. Customers should click here to go to the newest version.

Visible to Intel only — GUID: vgo1401246725374

Ixiasoft

View Details

6.1.1. Sink Word Alignment and Channel Deskew

The input stage of the sink is responsible for synchronizing the incoming parallel data channels correctly. The synchronization is split to two stages: word alignment and channel deskew.

Table 44. Synchronization Stages
Stage	Description
Word Alignment	TMDS Mode	Correctly aligns the incoming parallel data to word boundaries using bit-slip and pattern-matching technique. TMDS encoding does not guarantee unique control codes, but the core can still use the sequence of continuous symbols found in data and video preambles to align. The alignment algorithm searches for 8 consecutive 0×54 or 0×ab corresponding to the data and video preambles. Note: The preambles are also present in Digital Video Interface (DVI) coding. The alignment logic asserts a marker indicator when the 8 consecutive signals are detected. Similarly, the logic infers alignment loss when 8K symbol clocks elapse without a single marker assertion. Note: If you are using Intel® Arria® 10 or Intel® Cyclone® 10 GX devices, soft word alignment logic in the HDMI RX core is disabled for HDMI 2.0 resolution (data rate >3.4 Gbps). Hard transceiver PCS word alignment is used with some control logic to achieve faster word alignment with more optimized resource utilization. Refer to the design example user guides for more information. Note: If you are using Intel® Stratix® 10 devices, the HDMI RX core uses a new word alignment algorithm logic to achieve fast word alignment time for HDMI 2.0 resolution (data rate >3.4Gbps).
Word Alignment	FRL Mode	Correctly aligns the incoming parallel data to word boundaries using bit-slip and pattern-matching technique. FRL encoding uses unique Scrambler Reset (SR) and Start of Super Block (SSB) characters to achieve alignment. The FRL encoding loses lock when it does not receive the SR or SSB on one lane while other lane receive SR or SSB continuously for seven times.
Channel Deskew	When the data channels are aligned, the core then attempts to deskew each channel. The sink core deskews at the rising edge of the marker insertion. For every correct deskewed lane, the marker insertion will appear in all three TMDS encoded streams. The sink core deskews using three dual-clock FIFOs. The dual-clock FIFOs also synchronize all three data streams to the blue channel clock to be used later throughout the decoder core.

Figure 51. Channel Deskew DCFIFO ArrangementThe figure below shows the signal flow diagram of the deskew logic.

The FIFO read signal of the channels is normally asserted. The sink core deasserts a particular FIFO read signal if a marker appears at its output and not in the other two FIFO outputs. By deasserting, the sink core stalls the data stream for sufficient cycles to remove the channel skew. If any of the FIFO channels overflow, the sink core asserts a reset signal which propagates backwards to the word alignment logic.

Select Your Language

Using Intel.com Search

Quick Links

Recent Searches

Advanced Search

Only search in

HDMI Intel® FPGA IP User Guide

6.1.1. Sink Word Alignment and Channel Deskew