5.5. FRL Clocking Scheme

HDMI Intel® FPGA IP User Guide

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Date 6/26/2023

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5.5. FRL Clocking Scheme

The HDMI 2.1 design is not limited to run at the actual pixel clock, but the data can be processed at a faster clock rate. HDMI 2.1 data flow metering expects the data to be evenly distributed across the link bandwidth if the data runs at a faster clock rate.

The vid_valid signal at the HDMI TX core qualifies the validity of the data for every clock cycle. Due to the timing consideration on maximum FRL data rate, the transceiver width is set to 40 bits.

In the FRL clock domain, the TX core always processes the data in multiple of 18 bits because of the 16B/18B encoder in the FRL path. The FRL modules can process N (FRL char per clock) FRL characters in parallel. However, the FRL modules always process 8 or 16 FRL characters per clock due to timing considerations.

Hence, frl_clk frequency = (data rate per lane * number of lanes) / (FRL char per clock*18)

The number of lanes is always four.

For FRL rates 3–6, all four lanes carry the FRL characters.
For FRL rates 1 and 2, only 3 lanes carry the FRL characters and 1 lane is unused.

Similarly, in the vid_clk domain, the TX core processes data in multiples of pixels (24 bits) in parallel. You can configure the number of pixels to be processed in parallel through the pixels per clock GUI parameter. However, due to timing consideration and backward compatibility, the IP sets the pixels per clock to 2 when you turn off Support FRL, and to 8 when you turn on Support FRL. Because the actual pixel clock may differ based on different resolutions, you can configure vid_clk to the maximum frequency per the specified link rate according to the following calculation:

vid_clk frequency = max supported pixel clock / pixel per clock

Note: Because vid_clk can be asynchronous to frl_clk and ls_clk, you can set the vid_clk frequency according to the maximum pixel frequency of the highest allowed resolution divided by 8, to simplify the clocking scheme. Intel recommends that you set the vid_clk frequency to 225 MHz, as demonstrated in the HDMI Intel® FPGA IP FRL design example.

Table 41. Clock Frequencies for FRL Mode at Different Link Rates
FRL Rate	TX PLL Refclk Frequency (MHz)	TX Clkout (tx_clk) Frequency (MHz)		Maximum vid_clk Frequency (MHz)	frl_clk Frequency (MHz)
FRL Rate	TX PLL Refclk Frequency (MHz)	Intel® Arria® 10/ Intel® Stratix® 10 Devices	Intel Agilex® 7 F-tile Devices	Maximum vid_clk Frequency (MHz)	Intel® Arria® 10 Devices	Intel® Stratix® 10/ Intel Agilex® 7 F-tile Devices
1	100.00	75.00	150.00	50.00	41.665	83.33
2	100.00	150.00	300.00	75.00	83.33	166.67
3	100.00	150.00	300.00	120.00	83.33	166.67
4	100.00	200.00	400.00	150.00	111.11	222.22
5	100.00	250.00	500.00	200.00	138.89	277.78
6	100.00	300.00	600.00	225.00	166.67	333.33

Table 42. Clock Frequencies for TMDS Mode at Different Link Rates
TMDS_BIT_CLOCK_RATIO	TMDS Refclk (MHz)		TX PLL Refclk Frequency (MHz)		TX Clkout (tx_clk) Frequency (MHz)		ls_clk Frequency (MHz)		vid_clk Frequency (MHz)
TMDS_BIT_CLOCK_RATIO	Min	Max	Min	Max	Min	Max	Min	Max	Min	Max
TMDS_BIT_CLOCK_RATIO = 0	25.00	100.00	25.00	100.00	100.00	400.00	12.50	50.00	3.13	12.5
TMDS_BIT_CLOCK_RATIO = 0	100.00	340.00	100.00	340.00	50.00	170.00	50.00	170.00	12.50	42.50
TMDS_BIT_CLOCK_RATIO = 1	85.00	150.00	85.00	150.00	170.00	300.00	170.00	300.00	42.50	75.00

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5.5. FRL Clocking Scheme