HDMI Intel® FPGA IP User Guide

ID 683798
Date 6/26/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

9.4.2.3. F0_ACTIVE_LINE_COUNT (0x53)

Table 153.  F0_ACTIVE_LINE_COUNT (0x53)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
F0 active line count 15:0 RO The detected line count of the interlaced video field 0 or progressive video excluding blanking. 0x0