AN 809: SerialLite III IP Core Feature and Interface Differences between Stratix 10, Arria 10, and Stratix V

ID 683797
Date 6/19/2017
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IP Core Signals

Table 8.  IP Core Signal Differences in Stratix® 10, Arria® 10, and Stratix® V
Stratix® 10 Arria® 10 Stratix® V Comments
ready (ready_tx, ready_rx in Duplex IP) N/A N/A Stratix® 10: This is backpressure signal. In Source application, IP core backpressures user logic based on internal FIFO fill level. In Sink application, user logic backpressures IP core when not ready. Leave unconnected if unused.
err_interrupt (err_interrupt_tx, err_interrupt_rx in Duplex IP) N/A N/A Stratix® 10: Interrupt output. This signal indicates whether a transmit/receive has occurred in the current transmission. Leave unconnected if unused.
Avalon-MM Interface

12 + Ceil(Log2N) 1

10 + Ceil(Log2N) 1

9 phy_mgmt_addr port width.
Reset and Clock Interface
N/A core_reset core_reset Stratix® 10: There is no separate reset for the MAC (phy_mgmt_clk_reset resets both the MAC and PHY layers).

Arria® 10 and Stratix® V: Asynchronous reset input for the MAC layer. It resets the MAC except for the IOPLL ( Arria® 10)/fPLL ( Stratix® V) used in Standard Clocking Mode.



(interface_clock_reset_tx, interface_clock_reset_rx in Duplex)


(interface_clock_reset_tx, interface_clock_reset_rx in Duplex)
Arria® 10 and Stratix® V: IP core asserts this signal when the core_reset is high and deasserts this signal when the reset sequence is complete.

Available only in advanced clocking mode.

N/A reconfig_busy reconfig_busy Stratix® 10: Not used. Tie this signal to 0.

Arria® 10 and Stratix® V: When asserted, this signal indicates that a reconfiguration is in progress.

1 N: number of lanes.