Features

AN 809: SerialLite III IP Core Feature and Interface Differences between Stratix 10, Arria 10, and Stratix V

Download PDF

ID 683797

Date 6/19/2017

Version current

Public

Features

Table 1. Features Comparison
Stratix® 10	Arria® 10	Stratix® V	Comments
MAC and PHY Control and Status Registers (CSRs)	PHY Control and Status Registers	PHY Control and Status Registers	For more information about the registers, refer to the MAC and PHY register map in SerialLite III Sreaming IP Core User Guide.
17.4 Gbps	17.4 Gbps	14.1 Gbps	Maximum lane data rate

Table 2. Latency Measurement for Duplex Core ( Stratix® 10, Arria® 10, and Stratix® V)These latency values are TX-to-RX round trip latencies (time from `start_of_burst_tx` to `start_of_burst_rx`).
Device	Clocking Mode	Parameters		Latency (ns)
Device	Clocking Mode	Number of Lanes	Per-Lane Data Rate (Mbps)	Latency (ns)
Stratix® 10	Standard	6	12,500	304.128
Stratix® 10	Advanced	6	12,500	272.810
Arria® 10	Standard	5	17,400	174.064
Arria® 10	Advanced	5	17,400	154.996
Stratix® V	Standard	5	10,312.50	320.964
Stratix® V	Advanced	5	10,312.50	292.712

Table 3. Estimated Resource Utilization in ALMs for Duplex Configuration ( Stratix® 10, Arria® 10, and Stratix® V)
Device	Direction	Clocking Mode	Parameters			ALMs
Device	Direction	Clocking Mode	Number of Lanes	Per-Lane Data Rate (Mbps)	ECC	ALMs
Stratix 10	Duplex	Standard	16	17400	Disabled	5290
		Standard	16	17400	Enabled	9986
		Advanced	16	17400	Disabled	4725
		Advanced	16	17400	Enabled	9375
Arria 10	Duplex	Standard	24	17400	Disabled	6152
		Standard	24	17400	Enabled	9313
		Advanced	24	17400	Disabled	5833
		Advanced	24	17400	Enabled	8868
Stratix V	Duplex	Standard	24	10312.50	Disabled	8742
		Standard	24	10312.50	Enabled	14045
		Advanced	24	10312.50	Disabled	7550
		Advanced	24	10312.50	Enabled	12606