F-Tile Serial Lite IV Intel® FPGA IP Release Notes

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ID 683767
Date 4/01/2024
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1. F-Tile Serial Lite IV Intel® FPGA IP Release Notes
1. F-Tile Serial Lite IV Intel® FPGA IP Release Notes x
1.1. F-Tile Serial Lite IV Intel® FPGA IP v9.3.0 1.2. F-Tile Serial Lite IV Intel® FPGA IP v9.2.0 1.3. F-Tile Serial Lite IV Intel® FPGA IP v9.1.0 1.4. F-Tile Serial Lite IV Intel® FPGA IP v9.0.0 1.5. F-Tile Serial Lite IV Intel® FPGA IP v8.1.0 1.6. F-Tile Serial Lite IV Intel® FPGA IP v7.0.0 1.7. F-Tile Serial Lite IV Intel® FPGA IP v6.0.0 1.8. F-Tile Serial Lite IV Intel® FPGA IP v5.0.0 1.9. F-Tile Serial Lite IV Intel® FPGA IP v4.0.0 1.10. F-Tile Serial Lite IV Intel® FPGA IP v3.0.0 1.11. F-Tile Serial Lite IV Intel® FPGA IP v2.0.0
1. F-Tile Serial Lite IV Intel® FPGA IP Release Notes

1.10. F-Tile Serial Lite IV Intel® FPGA IP v3.0.0

Table 10.  v3.0.0 2021.10.04
Quartus® Prime Version Description Impact
21.3 Added a new parameter—RSFEC enabled on the other Serial Lite IV Simplex IP placed at the same FGT channel(s). —

In the F-Tile Serial Lite IV Intel® FPGA IP version 3.0.0, the default 165 MHz transceiver reference clock frequency for 56.1G data rate is no longer supported.

For IP designs that are generated from a previous version of the IP, the selected frequency may no longer be valid after IP upgrade. If you are upgrading designs that use from the previous IP version, you must review the selected reference clock frequency as it may no longer be valid. The IP upgrade automatically chooses a reference clock that is valid upon detecting that the selected frequency is invalid.

The Quartus® Prime Pro Edition software version 21.3 automatic IP upgrade may modify the transceiver reference clock in your design to a valid frequency, with a warning.
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