F-Tile Serial Lite IV Intel® FPGA IP Release Notes

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ID 683767
Date 4/01/2024
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1. F-Tile Serial Lite IV Intel® FPGA IP Release Notes
1. F-Tile Serial Lite IV Intel® FPGA IP Release Notes x
1.1. F-Tile Serial Lite IV Intel® FPGA IP v9.3.0 1.2. F-Tile Serial Lite IV Intel® FPGA IP v9.2.0 1.3. F-Tile Serial Lite IV Intel® FPGA IP v9.1.0 1.4. F-Tile Serial Lite IV Intel® FPGA IP v9.0.0 1.5. F-Tile Serial Lite IV Intel® FPGA IP v8.1.0 1.6. F-Tile Serial Lite IV Intel® FPGA IP v7.0.0 1.7. F-Tile Serial Lite IV Intel® FPGA IP v6.0.0 1.8. F-Tile Serial Lite IV Intel® FPGA IP v5.0.0 1.9. F-Tile Serial Lite IV Intel® FPGA IP v4.0.0 1.10. F-Tile Serial Lite IV Intel® FPGA IP v3.0.0 1.11. F-Tile Serial Lite IV Intel® FPGA IP v2.0.0
1. F-Tile Serial Lite IV Intel® FPGA IP Release Notes

1.9. F-Tile Serial Lite IV Intel® FPGA IP v4.0.0

Table 9.  v4.0.0 2021.12.13
Quartus® Prime Version Description Impact
21.4

Updated the building block setting for the FHT variants to accommodate Rules Based Configuration (RBC) requirements.

 To ensure a successful support-logic generation flow in your design, you must upgrade your IP core.
Updated the building block settings to accommodate the placements of both TX and RX on the same channel for the Avalon® memory-mapped interface simplex merging feature. —
Level Two Title