5G Polar Intel® FPGA IP User Guide

ID 683766
Date 4/01/2024

1. About the 5G Polar Intel® FPGA IP

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 2.0.2
The IP implements polar codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration in your wireless design. Polar codes support the high throughput for 5G new radio (NR).

The IP comprises:

  • Polar encoder and polar list decoder with a list size of 4 or 8
  • Interleaver and deinterleaver
  • CRC encoder and decoder
  • Bit allocator

Polar codes represent a new emerging class of error-correcting codes with power to approach the capacity of a discrete memoryless channel based on the recent invention by Arikan. This new code family is based on a channel polarization concept transforming independent channels into synthesized or polarized channels with different reliabilities: the good and the bad channels. The IP recursively applies such polarization transformation over the resulting channels such that the channels are polarized. The polarized channel encoder transmits information bits (i.e., free bits) over the noiseless channels while assigning fixed bits (i.e., frozen bits) to the noisy ones.