5G Polar Intel® FPGA IP User Guide

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ID 683766
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 5G Polar Intel® FPGA IP 2. Getting Started with the 5G Polar Intel® FPGA IP 3. Designing with the 5G Polar Intel® FPGA IP 4. 5G Polar Intel® FPGA IP Functional Description 5. 5G Polar IP User Guide Archive 6. Document Revision History for the 5G Polar Intel® FPGA IP User Guide
1. About the 5G Polar Intel® FPGA IP x
1.1. 5G Polar Intel® FPGA IP Features 1.2. 5G Polar Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G Polar Intel® FPGA IP 1.4. 5G Polar IP Performance and Resource Utilization
2. Getting Started with the 5G Polar Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G Polar IP Timeout Behavior
3. Designing with the 5G Polar Intel® FPGA IP x
3.1. 5G Polar IP Directory Structure 3.2. Generating a 5G Polar IP 3.3. Simulating the 5G Polar IP with RTL Simulators 3.4. Simulating the 5G Polar IP with MATLAB 3.5. Simulating the 5G Polar IP with the C-model
3.3. Simulating the 5G Polar IP with RTL Simulators x
3.3.1. Simulation Results for the 5G Polar IP
4. 5G Polar Intel® FPGA IP Functional Description x
4.1. 5G Polar IP Signals 4.2. 5G Polar IP Throughput and Latency
1. About the 5G Polar Intel® FPGA IP
2. Getting Started with the 5G Polar Intel® FPGA IP
3. Designing with the 5G Polar Intel® FPGA IP
4. 5G Polar Intel® FPGA IP Functional Description
5. 5G Polar IP User Guide Archive
6. Document Revision History for the 5G Polar Intel® FPGA IP User Guide

4. 5G Polar Intel® FPGA IP Functional Description

The IP includes an encoder and decoder.
Table 7.  O-RAN IP Definitions
Symbol Definition
A Number of message bits
L Number of CRC bits
N Number of polar coded bits (Polar encoder output length)
n pc Number of parity check bits
E Number of rate-matching output bits
K Number of bits to encode (Polar encoder input length)
LLR Log likelihood ratio
Table 8.  Parameter Requirements

The table shows how the parameters, including A, L, K, npc and N, must agree.

Code block length N
Frozen bits N-K-n pc Non-frozen bits K+n pc
Parity check bits n pc Interleaver bits K
CRC bits L Message bits A
Table 9.  Configuration in 3GPP 5G NR specification TS38.212The table shows the parts of 3GPP 5G NR specs TS38.212 and TS38.214 that the IP complies with:
Downlink Uplink
PDCCH PBCH PUCCH/PUSCH
12 ≤ A ≤ 140 A = 32

12 ≤ A ≤ 19

20 ≤ A ≤ 1012

(no segmentation)
36 < E ≤ 8192 E = 864

21 < E≤ 8192

31 < E≤ 8192

L = 24

(crc24c with RNTI)

L = 24

(crc24c)

L = 6

(crc6)

L = 11

(crc11)
n pc = 0 n pc = 3 n pc = 0
Interleaver is ON Interleaver is OFF
Nmax = 512 Nmax = 1024
  • PDCCH: zero pad message bits to reach 12 bits, when A<12
  • Uplink: segmentation is enabled for A>1012
  • E > K+n pc for all cases.

If you mistakenly feed malformed Avalon streaming sink packets into the IP that cause it to produce no source data and it reaches timeout, de-assert rstn to soft reset the IP. No source data and reaching timeout means missing sink_sop, missing sink_eop, packet length (the amount of data between sink_sop and sink_eop) not consistent with input parameters). For the expected latency between sink and source, refer to 5G Polar Throughput and Latency.

Figure 12. 5G Polar Encoder

The encoder comprises a CRC encoder, an interleaver with a frozen bit and parity check bit insertion block, and a polar encoder. The encoder accepts the input message data and optionally appends the CRC bits based on the CRC type. Then the interleaver optionally shuffles the result and the encoder encodes the message.

Figure 13. 5G Polar Decoder

The decoder comprises a polar list decoder (list size of 4 or 8), a deinterleaver, and a CRC decoder. The polar list decoder is based on the successive cancellation decoding algorithm. The compile-time parameter NUM_LIST sets the list size. The list decoder parallelizes NUM_LIST computations of each decoding step of the algorithm. It generates 2*NUM_LIST temporary candidates. It performs a sorting to keep the better NUM_LIST candidates to proceed to the next decoding step, until it finishes all the decoding steps. The polar list decoder first decodes the received messages and provides the total number of NUM_LIST decoded candidates, and it provides the index of the best candidate. The deinterleaver optionally reverts the encoder interleaving for all candidates. If you turn off the CRC, the IP produces the best candidate as determined by the polar list decoder. If you turn on the CRC, all candidates go through the CRC decoder so that the IP produces the candidate with the best CRC decoding. The result contains CRC bits.

Figure 14. Downlink Encoder with Bit Allocation

The downlink encoder with bit allocation has a dedicated downlink bit allocator. More specifically, the CRC encoder and the interleaver are always enabled. The bit allocator and CRC encoder can operate at the same time, when a new packet comes in. The latency of the bit allocator is smaller than that of the CRC encoder in any cases. Therefore, the overall latency with bit allocation keeps the same to that of encoder only. The latency of the downlink bit allocator is.

  • L_pipe: latency of precomputing and pipelining
    • constant 18 cycles
  • L_fro: latency of finding frozen bits location
    • ceil(K/4) cycles, when K/E <= 7/16 or E>N
    • ceil((N-E+K)/4) cycles, when K/E > 7/16
  • L_ba: latency of bit allocation
    • L_ba = L_pipe + L_fro
Figure 15. Uplink Decoder with Bit Allocation

The uplink decoder with bit allocation has a dedicated uplink bit allocator. More specifically, the CRC decoder is always enabled and the de-interleaver is always disabled. Bit allocation must be completed before the decoder can start to process a packet. The overall latency with bit allocation is longer than that of decoder without the bit allocation. However, the bit allocation can start to process a new packet, while the decoder processes the current packet. Therefore, the decoding process can hide the latency of the bit allocation. The latency of uplink bit allocation is.

  • L_pipe: latency of precomputing and pipelining
    • constant 18 cycles
  • L_fro: latency of finding frozen bits location
    • ceil((K + n pc )/4) cycles, when K/E <= 7/16 or E>N
    • ceil((N-E+K+n pc )/4) cycles, when K/E > 7/16
  • L_pc: latency of finding parity check bits location
    • upto 39 cycles, when A <=19
    • 0 cycles, when A >19
  • L_ba: latency of bit allocation
    • L_ba = L_pipe + L_fro + L_pc

Where (K + n pc ) is total nonfrozen bits length, which is the sum of

  • message bits length, A
  • CRC length, L = 6 or 11
  • number of parity check bits, n pc = 3 or 0

Section Content
5G Polar IP Signals
5G Polar IP Throughput and Latency

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