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1. Intel® Stratix® 10 Configuration User Guide
2. Intel® Stratix® 10 Configuration Details
3. Intel® Stratix® 10 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Intel® Stratix® 10 Configuration Features
7. Intel® Stratix® 10 Debugging Guide
8. Intel® Stratix® 10 Configuration User Guide Archives
9. Document Revision History for the Intel® Stratix® 10 Configuration User Guide
2.1. Intel® Stratix® 10 Configuration Timing Diagram
2.2. Configuration Flow Diagram
2.3. Device Response to Configuration and Reset Events
2.4. Additional Clock Requirements for HPS, PCIe* , eSRAM, and HBM2
2.5. Intel® Stratix® 10 Configuration Pins
2.6. Configuration Clocks
2.7. Maximum Configuration Time Estimation
2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
3.1.7.4.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. PFL II IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. PFL II IP Recommended Design Constraints for using CFI Flash
3.1.7.4.4. PFL II IP Recommended Constraints for Other Input Pins
3.1.7.4.5. PFL II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Intel® Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Intel® Stratix® 10 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. SDM Debug Toolkit Overview
7.5. Configuration Pin Differences from Previous Device Families
7.6. Configuration File Format Differences
7.7. Understanding SEUs
7.8. Reading the Unique 64-Bit CHIP ID
7.9. E-Tile Transceivers May Fail To Configure
7.10. Understanding and Troubleshooting Configuration Pin Behavior
3.1.7.1.5. Implementing Page Mode and Option Bits in the CFI Flash Memory Device
The following figure shows a sample layout of a .pof with three pages. The end addresses depend on the density of the flash memory device. For different density devices refer to the Byte Address Range for CFI Flash Memory Devices with Different Densities table below. The option bits follow the configuration data in memory.
Figure 24. Implementing Page Mode and Option Bits in the CFI Flash Memory Device
The following figure shows the layout of the option bits for a single page. Because the start address must be on an 8 KB boundary, bits 0-12 of the page start address are set to zero and are not stored in the option bits.
Figure 25. Page Start Address, End Address, and Page-Valid Bit Stored as Option BitsThe Page-Valid bits indicate whether each page is successfully programmed. The PFL II IP core sets the Page-Valid bits after successfully programming the pages.
CFI Device (Megabit) | Address Range |
---|---|
8 | 0x0000000–0x00FFFFF |
16 | 0x0000000–0x01FFFFF |
32 | 0x0000000–0x03FFFFF |
64 | 0x0000000–0x07FFFFF |
128 | 0x0000000–0x0FFFFFF |
256 | 0x0000000–0x1FFFFFF |
512 | 0x0000000–0x3FFFFFF |
1024 | 0x0000000–0x7FFFFFF |