Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. Remote Update Intel® FPGA IP User Guide
1. Remote Update Intel® FPGA IP User Guide x
1.1. Release Information for Remote Update Intel® FPGA IP 1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP 1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices 1.5. Cyclone IV and Intel Cyclone 10 LP Devices 1.6. Flash Memory Programming Files 1.7. Design Examples 1.8. Remote Update Intel® FPGA IP User Guide Archives 1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
1.3.1. Remote System Configuration Mode 1.3.2. Remote System Configuration Components 1.3.3. Parameter Settings 1.3.4. Ports 1.3.5. Parameters 1.3.6. Avalon® Memory-Mapped Interface 1.3.7. Enabling Remote System Upgrade Circuitry 1.3.8. Generating Initial RSU Image
1.3.1. Remote System Configuration Mode x
1.3.1.1. Remote System Upgrade State Machine
1.3.1.1. Remote System Upgrade State Machine x
1.3.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
1.3.6. Avalon® Memory-Mapped Interface x
1.3.6.1. Control Status Register Signals 1.3.6.2. Register Map
1.3.6.1. Control Status Register Signals x
1.3.6.1.1. Control Status Register Write Operation 1.3.6.1.2. Control Status Register Read Operation 1.3.6.1.3. Operations Example Waveforms
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices x
1.4.1. Remote System Configuration Mode 1.4.2. Remote System Configuration Components 1.4.3. Parameter Settings 1.4.4. Ports 1.4.5. Parameters 1.4.6. Avalon® Memory-Mapped Interface 1.4.7. Enabling Remote System Upgrade Circuitry
1.4.6. Avalon® Memory-Mapped Interface x
1.4.6.1. Control Status Register Signals 1.4.6.2. Register Map
1.4.6.1. Control Status Register Signals x
1.4.6.1.1. Control Status Register Write Operation 1.4.6.1.2. Control Status Register Read Operation
1.5. Cyclone IV and Intel Cyclone 10 LP Devices x
1.5.1. Remote System Configuration Mode 1.5.2. Remote System Configuration Components 1.5.3. Parameter Settings 1.5.4. Ports 1.5.5. Parameters 1.5.6. Remote Update Operation 1.5.7. Avalon® Memory-Mapped Interface 1.5.8. Enabling Remote System Upgrade Circuitry
1.5.7. Avalon® Memory-Mapped Interface x
1.5.7.1. Control Status Register Signals 1.5.7.2. Register Map 1.5.7.3. Read Source Mapping
1.5.7.1. Control Status Register Signals x
1.5.7.1.1. Control Status Register Write Operation 1.5.7.1.2. Control Status Register Read Operation
1.7. Design Examples x
1.7.1. Intel Arria 10 Remote Update Design Example 1.7.2. Cyclone® V Remote Update Design Example
1. Remote Update Intel® FPGA IP User Guide

1.3.2. Remote System Configuration Components

Table 2.  Remote System Configuration Components in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Components Details
Page mode feature

The dedicated 32-bit start address register PGM[31..0] holds the start address.

Factory configuration

Factory configuration can be set as the default configuration setup depending on the address pointer set.

The factory configuration loads into the device upon power-up.

If a system encounters an error while loading application configuration data or if the device reconfigures due to nCONFIG assertion, the device loads the factory configuration. The remote system configuration register determines the reason for factory configuration. Based on this information, the factory configuration determines which application configuration to load.

Application configuration

Application configuration can be the default configuration setup depending on the address pointer set.

The application configuration loads into the device upon power-up.

The application configuration is the configuration data from a remote source and the data is stored in different locations or pages of the memory storage device, excluding the factory page.

Watchdog timer

A watchdog timer is a circuit that determines the functionality of another mechanism. The watchdog timer functions like a time delay relay that remains in the reset state while an application runs properly.

Intel® Arria® 10 and Intel® Cyclone® 10 GX devices are equipped with a built-in watchdog timer for remote system configuration to prevent a faulty application configuration from indefinitely stalling the device.

The timer is a 29-bit counter, but you use only the upper 12 bits (left-most or most-significant bits) to set the value for the watchdog timer.

The timer begins counting after the device goes into user mode. To ensure the application configuration is valid, you must continuously reset the watchdog reset_timer within a specific duration during user mode operation.

If the application configuration does not reset the user watchdog timer before time expires, the dedicated circuitry reconfigures the device with the factory configuration and resets the user watchdog timer.

Remote update sub-block

The remote update sub-block manages the remote configuration feature. A remote configuration state machine controls this sub-block. This sub-block generates the control signals required to control the various configuration registers.

Remote configuration registers

The remote configuration registers keep track of page addresses and the cause of configuration errors. You can control both the update and shift registers. The status and control registers are controlled by internal logic, but are read via the shift register. The control register is 38-bits wide.

For details about configuration registers, refer to the Configuration, Design Security, and Remote System Upgrades chapter in the Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook or the Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook.

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