Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. Remote Update Intel® FPGA IP User Guide
1. Remote Update Intel® FPGA IP User Guide x
1.1. Release Information for Remote Update Intel® FPGA IP 1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP 1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices 1.5. Cyclone IV and Intel Cyclone 10 LP Devices 1.6. Flash Memory Programming Files 1.7. Design Examples 1.8. Remote Update Intel® FPGA IP User Guide Archives 1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
1.3.1. Remote System Configuration Mode 1.3.2. Remote System Configuration Components 1.3.3. Parameter Settings 1.3.4. Ports 1.3.5. Parameters 1.3.6. Avalon® Memory-Mapped Interface 1.3.7. Enabling Remote System Upgrade Circuitry 1.3.8. Generating Initial RSU Image
1.3.1. Remote System Configuration Mode x
1.3.1.1. Remote System Upgrade State Machine
1.3.1.1. Remote System Upgrade State Machine x
1.3.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
1.3.6. Avalon® Memory-Mapped Interface x
1.3.6.1. Control Status Register Signals 1.3.6.2. Register Map
1.3.6.1. Control Status Register Signals x
1.3.6.1.1. Control Status Register Write Operation 1.3.6.1.2. Control Status Register Read Operation 1.3.6.1.3. Operations Example Waveforms
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices x
1.4.1. Remote System Configuration Mode 1.4.2. Remote System Configuration Components 1.4.3. Parameter Settings 1.4.4. Ports 1.4.5. Parameters 1.4.6. Avalon® Memory-Mapped Interface 1.4.7. Enabling Remote System Upgrade Circuitry
1.4.6. Avalon® Memory-Mapped Interface x
1.4.6.1. Control Status Register Signals 1.4.6.2. Register Map
1.4.6.1. Control Status Register Signals x
1.4.6.1.1. Control Status Register Write Operation 1.4.6.1.2. Control Status Register Read Operation
1.5. Cyclone IV and Intel Cyclone 10 LP Devices x
1.5.1. Remote System Configuration Mode 1.5.2. Remote System Configuration Components 1.5.3. Parameter Settings 1.5.4. Ports 1.5.5. Parameters 1.5.6. Remote Update Operation 1.5.7. Avalon® Memory-Mapped Interface 1.5.8. Enabling Remote System Upgrade Circuitry
1.5.7. Avalon® Memory-Mapped Interface x
1.5.7.1. Control Status Register Signals 1.5.7.2. Register Map 1.5.7.3. Read Source Mapping
1.5.7.1. Control Status Register Signals x
1.5.7.1.1. Control Status Register Write Operation 1.5.7.1.2. Control Status Register Read Operation
1.7. Design Examples x
1.7.1. Intel Arria 10 Remote Update Design Example 1.7.2. Cyclone® V Remote Update Design Example
1. Remote Update Intel® FPGA IP User Guide

1.3.8. Generating Initial RSU Image

To convert .sof files to one .jic/.rpd files and to generate the initial RSU image, follow these steps:

On the File menu, click Convert Programming File and select the details as shown below:
  • Programming File type: JTAG Indirect Configuration File (.jic).
  • Configuration Device: <Select the Configuration Device used in your board>.
  • Mode: Select either Active Serial/Active Serial x4.
  • File_name: Set the file name and your desired location.
  • Optional:
    • Check the Create Memory File to generate the .map file
    • Check the Create config data RPD to generate the .rpd file
  • Flash loader: Click Add Device, select Arria 10 and choose the Device name used in your design
  • SOF DATA PAGE_0: click Add File and assign Factory image (.sof) to Page_0. Assign the factory image to PAGE_0 and set the start address for the factory image to 0x20 to ensure the device is able to fall back to the factory image after the user watchdog timer has timeout or when the device fails to load an application image.
  • Click Add Sof Page to add SOF Data Page_1. You can add more SOF Data Page according to the number of application images in this initial RSU image.
  • SOF DATA PAGE_1: click Add File and select the application image file (.sof).
  • Setting Boot Page Selection for enabling the device to boot either from factory image or application image
    • To select the boot page, click the Option/Boot Info button in Convert Programming File.
    • In the Options window, select the page available from the Boot from page drop down menu.
    • By default, the page number will be set at Page_0.
    • To allow the FPGA to boot directly from application image (DTA), change the page number to Page_1 and so on.
  • Click Generate.
  • Click OK when the dialog box of .jic file successfully generated appears.
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