Intel® Agilex™ Configuration User Guide

ID 683673
Date 1/14/2022

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2.4. Additional Clock Requirements for HPS and Transceivers

The Intel® Agilex™ device has specific clock requirements for transceivers and HPS EMIF IP. These clock requirements must be met before the FPGA configuration begins.

FPGA Configuration

To avoid configuration failures, the Intel® Agilex™ device requires additional clocks for transceivers, HPS EMIF IP, and all E-tile variants. You must provide a free-running, stable reference clock to these blocks before configuration begins. The clock frequencies must match the frequency settings specified in the Intel® Quartus® Prime software during configuration. This reference clock is in addition to the configuration clock requirements for an internal or external oscillator described in OSC_CLK_1 Requirements.

These blocks and their specific clock names are as listed below.
  • HPS reference clock: HPS_OSC_CLK, when HPS enabled 3
  • HPS EMIF: pll_ref_clk
  • E-tile transceivers: REFCLK_GXE
Note: The transceiver power supplies must be at nominal levels for successful configuration. You can use the VCC and VCCP power supplies for limited transceiver channel testing. Designs that include many transceivers require an auxiliary power supply to operate reliably.
Note: A free-running and stable reference clock to the R-tile transceiver is not mandatory for configuring the FPGA for the first time after the device is powered on. The reference clock to R-tile transceiver REFCLK_GXR must be on for a subsequent configuration when the device is in user mode.

Intel® Quartus® Prime Pro Edition software allows you to configure the HPS prior to FPGA configuration. To enable this option, select HPS First in the Assignments > Device > Device and Pin Options > Configuration > HPS/FPGA Configuration order dialog box.

HPS First Configuration

Intel® Agilex™ devices have the option of booting the HPS before configuring the FPGA core logic. This method is known as the HPS first configuration. When you choose this option in the Intel® Quartus® Prime Pro Edition software, the following clocks must be operational prior to the FPGA I/O, HPS I/O, and HPS boot, also called a phase 1 configuration:
  • HPS reference clock: HPS_OSC_CLK
  • HPS EMIF (when in use): pll_ref_clk
  • E-tile transceivers: REFCLK_GXE

The remaining clocks specified in the FPGA Configuration must be fully operational prior the FPGA core logic configuration, also called phase 2 configuration.

3 If you use the FPGA to HPS free clock as the HPS PLL reference clock, the HPS_OSC_CLK clock may not be required.