1. Intel® Agilex™ Configuration User Guide 2. Intel® Agilex™ Configuration Details 3. Intel® Agilex™ Configuration Schemes 4. Including the Reset Release Intel® FPGA IP in Your Design 5. Remote System Update (RSU) 6. Intel® Agilex™ Configuration Features 7. Intel® Agilex™ Debugging Guide 8. Intel® Agilex™ Configuration User Guide Archives 9. Document Revision History for the Intel® Agilex™ Configuration User Guide
2.1. Intel® Agilex™ Configuration Timing Diagram 2.2. Configuration Flow Diagram 2.3. Device Response to Configuration and Reset Events 2.4. Additional Clock Requirements for HPS and Transceivers 2.5. Intel® Agilex™ Configuration Pins 2.6. Configuration Clocks 2.7. Intel® Agilex™ Configuration Time Estimation 2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types 3.1.2. Enabling Avalon-ST Device Configuration 3.1.3. The AVST_READY Signal 3.1.4. RBF Configuration File Format 3.1.5. Avalon-ST Single-Device Configuration 3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme 3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
22.214.171.124.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins 126.96.36.199.2. PFL II IP Recommended Design Constraints for Using QSPI Flash 188.8.131.52.3. PFL II IP Recommended Design Constraints for using CFI Flash 184.108.40.206.4. PFL II IP Recommended Constraints for Other Input Pins 220.127.116.11.5. PFL II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types 3.2.2. AS Single-Device Configuration 3.2.3. AS Using Multiple Serial Flash Devices 3.2.4. AS Configuration Timing Parameters 3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines 3.2.6. Programming Serial Flash Devices 3.2.7. Serial Flash Memory Layout 3.2.8. AS_CLK 3.2.9. Active Serial Configuration Software Settings 3.2.10. Intel® Quartus® Prime Programming Steps 3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description 5.2. Guidelines for Performing Remote System Update Functions for Non-HPS 5.3. Commands and Responses 5.4. Quad SPI Flash Layout 5.5. Generating Remote System Update Image Files Using the Programming File Generator 5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image 5.6.3. Programming Flash Memory with the Initial Remote System Update Image 5.6.4. Reconfiguring the Device with an Application or Factory Image 5.6.5. Adding an Application Image 5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist 7.2. Intel® Agilex™ Configuration Architecture Overview 7.3. Understanding Configuration Status Using quartus_pgm command 7.4. Configuration File Format Differences 7.5. Understanding SEUs 7.6. Reading the Unique 64-Bit CHIP ID 7.7. E-Tile Transceivers May Fail To Configure 7.8. Understanding and Troubleshooting Configuration Pin Behavior
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
5.5.3. Generating a Factory Update Image
You can generate the factory update image from the command line directly, by running the quartus_pfg with the following arguments:
quartus_pfg -c fpga.sof factory_update.rpd -o mode=ASX4 -o start_address=<address> -o bitswap=ON -o rsu_upgrade=ON
Note: The rsu1.tcl script that Intel provides performs the bit swap operation. Consequently, if you are using this script, set bitswap=OFF in the command above.Alternatively, you can use the Intel® Quartus® Prime Pro Edition Programming File Generator to generate a factory update image (.rpd). You can use this image to update the decision firmware, decision firmware data, and the factory image.
Note: The .rpd to program flash memory includes firmware pointer information for image addresses. You must use the Programming File Generator to generate the .rpd for flash devices.On the File menu, click Programming File Generator.
- Select Intel® Agilex™ from the Device family drop-down list.
- Select the configuration mode from the Configuration mode drop-down list. The current Intel® Quartus® Prime only supports the RSU feature in the Active Serial x4 configuration mode.
- On the Output Files tab, assign the Output directory and Name.
- Select the .rpd output file type.
- Click the Edit… button and assign the Start address for the factory update image in flash memory. You do not have to create a separate partition for the factory update image. The factory update image typically includes the minimum amount of logic necessary to successfully debug your design if your application image fails to load. Consequently the Start address can be the sector boundary of unused space in flash memory. This Start address must match the starting address of the target sector in flash memory. If the address is incorrect, the image does not load when the host tries to use this image as a backup image.
Note: If unused space is not available, you can use an application image space other than application image 1. In this case after the update operation completes you must restore the application image by writing the associated application image (.rpd) to the application slot.Figure 73. Specifying Parameters for Single .rpd Stored in Flash Memory
- By default, the .rpd file type is little-endian. If you are using a third-party programmer that does not support the little-endian format, set Bit swap to On to generate the .rpd file in big endian format.
Note: The rsu1.tcl script that Intel provides performs the bit swap operation. Consequently, if you are using this script, set Bit swap to Off.
- On the Input Files tab, click Add Bitstream. If necessary, change the Files of type to SRAM Object File (*.sof). Then, select factory image .sof file and click Open.
Figure 74. Specify the .sof File
- Select the .sof and then click Properties. Turn On Generate RSU factory update image. Specify the Bootloader file.
Note: You only have to specify the Bootloader file for Intel® Agilex™ SX devices.Figure 75. Turn On Remote System Firmware Upgrade
- Click Generate to generate the RSU programming files. You can now update the Intel® Agilex™ firmware. You can save the configuration in a .pfg file for later use.