Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 2/10/2023

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Document Table of Contents

3.4.2. RX Reset and Initialization Sequence

The RX reset sequence for Serial Lite IV Intel® FPGA IP is as follows:
  1. Assert rx_pcs_fec_phy_reset_n, rx_core_rst_n, and reconfig_reset simultaneously to reset the custom PCS, MAC, and reconfiguration blocks. Release the custom PCS (rx_pcs_fec_phy_reset_n) and reconfiguration reset (reconfig_reset) after 200 ns to ensure the blocks are properly reset.
  2. The IP then asserts the phy_rx_pcs_ready signal after the custom PCS reset is released, to indicate RX PHY is ready for transmission.
  3. The rx_core_rst_n signal deasserts after phy_rx_pcs_ready signal goes high.
  4. The IP starts the lane alignment process after the RX MAC reset is released and upon receiving ALIGN paired with START/END or END/START CWs.
  5. The RX deskew block asserts the rx_link_up signal once alignment for all lanes has complete.
  6. The IP then asserts the rx_link_up signal to the user logic to indicate that the RX link is ready to start data reception.
Figure 24. RX Reset and Initialization Timing Diagram