Nios® V Processor Reference Manual

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ID 683632
Date 7/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Nios® V/c Processor 3. Nios® V/m Processor 4. Nios® V/g Processor 5. Nios V Processor Reference Manual Archives 6. Document Revision History for the Nios® V Processor Reference Manual
1. Overview x
1.1. Quartus® Prime Software Support
2. Nios® V/c Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General-Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Reset and Debug Signals 2.3.4. Memory and I/O Organization 2.3.5. Error Correction Code (ECC)
2.3.4. Memory and I/O Organization x
2.3.4.1. Instruction and Data Buses 2.3.4.2. Address Map
2.3.4.1. Instruction and Data Buses x
2.3.4.1.1. Instruction Manager Port 2.3.4.1.2. Data Manager Port
2.4. Programming Model x
2.4.1. Privilege Levels
2.5. Core Implementation x
2.5.1. Instruction Set Reference
3. Nios® V/m Processor x
3.1. Processor Performance Benchmarks 3.2. Processor Pipeline 3.3. Processor Architecture 3.4. Programming Model 3.5. Core Implementation
3.1. Processor Performance Benchmarks x
3.1.1. Pipelined 3.1.2. Non-pipelined
3.2. Processor Pipeline x
3.2.1. Pipelined Architecture 3.2.2. Non-pipelined Architecture
3.3. Processor Architecture x
3.3.1. General-Purpose Register File 3.3.2. Arithmetic Logic Unit 3.3.3. Reset and Debug Signals 3.3.4. Control and Status Registers 3.3.5. Trap Controller 3.3.6. Memory and I/O Organization 3.3.7. RISC-V based Debug Module 3.3.8. Error Correction Code (ECC)
3.3.5. Trap Controller x
3.3.5.1. Exception Handling 3.3.5.2. Interrupt Handling
3.3.5.2. Interrupt Handling x
3.3.5.2.1. Timer and Software Interrupt Module
3.3.6. Memory and I/O Organization x
3.3.6.1. Instruction and Data Buses 3.3.6.2. Address Map
3.3.6.1. Instruction and Data Buses x
3.3.6.1.1. Instruction Manager Port 3.3.6.1.2. Data Manager Port
3.3.7. RISC-V based Debug Module x
3.3.7.1. Debug Mode 3.3.7.2. Halt from Debug Module 3.3.7.3. Trigger 3.3.7.4. Abstract Commands in Debug Mode 3.3.7.5. Hardware/Software Interface
3.4. Programming Model x
3.4.1. Privilege Levels 3.4.2. Control and Status Registers (CSR) Mapping
3.4.1. Privilege Levels x
3.4.1.1. Machine Mode (M-mode) 3.4.1.2. Debug Mode (D-mode)
3.4.2. Control and Status Registers (CSR) Mapping x
3.4.2.1. Control and Status Register Field
3.5. Core Implementation x
3.5.1. Instruction Set Reference
4. Nios® V/g Processor x
4.1. Processor Performance Benchmarks 4.2. Processor Pipeline 4.3. Processor Architecture 4.4. Programming Model 4.5. Core Implementation
4.3. Processor Architecture x
4.3.1. General-Purpose Register File 4.3.2. Arithmetic Logic Unit 4.3.3. Multipy and Divide Units 4.3.4. Floating-Point Unit 4.3.5. Custom Instruction 4.3.6. Reset and Debug Signals 4.3.7. Control and Status Registers 4.3.8. Trap Controller 4.3.9. Memory and I/O Organization 4.3.10. RISC-V based Debug Module 4.3.11. Error Correction Code (ECC)
4.3.4. Floating-Point Unit x
4.3.4.1. IEEE 754 Exception Conditions 4.3.4.2. Floating Point Operations
4.3.4.2. Floating Point Operations x
4.3.4.2.1. Floating Point Classification
4.3.8. Trap Controller x
4.3.8.1. Exception Controller 4.3.8.2. Interrupt Controller
4.3.8.2. Interrupt Controller x
4.3.8.2.1. Timer and Software Interrupt Module
4.3.9. Memory and I/O Organization x
4.3.9.1. Instruction and Data Buses 4.3.9.2. Address Map 4.3.9.3. Cache Memory 4.3.9.4. Tightly Coupled Memory
4.3.9.1. Instruction and Data Buses x
4.3.9.1.1. Instruction Manager Port 4.3.9.1.2. Data Manager Port
4.3.9.3. Cache Memory x
4.3.9.3.1. Instruction Cache 4.3.9.3.2. Data Cache 4.3.9.3.3. Configurable Cache Memory 4.3.9.3.4. Bypassing Cache (Peripheral Region) 4.3.9.3.5. Using Cache Memory Effectively
4.3.9.4. Tightly Coupled Memory x
4.3.9.4.1. Instruction and Data Tightly Coupled Memory 4.3.9.4.2. Accessing Tightly Coupled Memory 4.3.9.4.3. Using Tightly Coupled Memory Effectively
4.3.10. RISC-V based Debug Module x
4.3.10.1. Debug Mode 4.3.10.2. Halt from Debug Module 4.3.10.3. Trigger 4.3.10.4. Abstract Commands in Debug Mode 4.3.10.5. Hardware/Software Interface
4.4. Programming Model x
4.4.1. Privilege Levels 4.4.2. Control and Status Registers (CSR) Mapping
4.4.1. Privilege Levels x
4.4.1.1. Machine Mode (M-mode) 4.4.1.2. Debug Mode (D-mode)
4.4.2. Control and Status Registers (CSR) Mapping x
4.4.2.1. Control and Status Register Field
4.5. Core Implementation x
4.5.1. Instruction Set Reference
1. Overview
2. Nios® V/c Processor
3. Nios® V/m Processor
4. Nios® V/g Processor
5. Nios V Processor Reference Manual Archives
6. Document Revision History for the Nios® V Processor Reference Manual

3.4.2.1. Control and Status Register Field

The value in the each CSR registers determines the state of the Nios® V/m processor. The field descriptions are based on the RISC-V specification.

Table 37.  Machine Status Register FieldsThe mstatus register is a 32-bit read-write register that keeps track of and controls the hart’s current operating state.
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SD 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 MPP[1:0] 0 0 MPIE 0 0 0 MIE 0 0 0
The following bitfields are read-only 0 because:
  • Bit 22 (TSR = 0): S-mode is not supported
  • Bit 21 (TW = 0): There are no modes less privileged than M-mode.
  • Bit 20 (TVM = 0): S-mode is not supported
  • Bit 19 (MXR = 0): S-mode is not supported
  • Bit 18 (SUM = 0): S-mode and U-mode are not supported
  • Bit 17 (MPRV = 0): U-mode is not supported
  • Bit 16 and Bit 15 (XS[1:0] = 0): S-mode is not supported
  • Bit 14 and Bit 13 (FS[1:0] = 0): “F” extension for Single-Precision Floating-Point is not supported
  • Bit 10 and Bit 9 (VS[1:0] = 0): S-mode is not supported
  • Bit 8 (SPP = 0): S-mode is not supported
  • Bit 6 (UBE = 0): U-mode is not supported
  • Bit 5 (SPIE = 0): S-mode is not supported
  • Bit 1 (SIE = 0): S-mode is not supported
Table 38.  Machine ISA Register FieldsThe misa CSR is a read-write register reporting the ISA supported by the hart.
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MXL[1:0] 0 Extension[25:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Extension[25:0]
Table 39.  Machine Interrupt-Enable Register FieldsThe mie register is a 32-bit read-write register that contains interrupt enable bits. This core does not support supervisor or user modes. Thus, any interrupt related to these modes is read-only 0.
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Platform Interrupt[15:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 MEIE 0 0 0 MTIE 0 0 0 MSIE 0 0 0
Table 40.  Machine Trap-Handler Base Address Register FieldsThe mtvec register is a 32-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Base[31:2]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Base[31:2] Mode
Table 41.  Machine Exception Program Counter Register FieldsThe mepc register is a 32-bit read-write register that holds the addresses of the instruction that was interrupted or that encountered the exception when a trap is taken into M-mode.
Bit Field
31 30 29 28 27 26 25 ... 6 5 4 3 2 1 0
mepc
Table 42.  Machine Trap Cause Register FieldsThe mcause register is a 32-bit read-write register that hold the code indicating the event that caused the trap when a trap is taken into M-mode.
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Interrupt Exception code [30:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Exception code [15:0]
Table 43.  Machine Trap Value Register Fields The mtval register is a 32-bit read-write register that is written with exception-specific information to assist software in handling the trap when a trap is taken into M-mode.
Bit Field
31 30 29 28 27 26 25 ... 6 5 4 3 2 1 0
mtval
Table 44.  Machine Interrupt-Pending Register FieldsThe mip register is a 32-bit read/write register containing information on pending interrupts. This core does not support supervisor or user modes. Thus, any interrupt related to these modes is read-only 0.
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Platform Interrupt[15:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 MEIP 0 0 0 MTIP 0 0 0 MSIP 0 0 0
Table 45.  Trigger Select Register FieldsThe tselect register is a 32-bit read/write register that selects the current trigger is accessible by other trigger register.
Bit Field
31 30 29 28 27 26 25 ... 6 5 4 3 2 1 0
tselect
Table 46.  Trigger Data 1 (Match Control) Register FieldsThe tdata1 (mcontrol) register is a 32-bit read/write register containing information on the trigger type, tdata registers accessibility, and trigger implementation. This core does not support supervisor or user modes. Thus, any bitfield related to these modes is read-only 0.
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
type=2 dmode maskmax hit select timing sizelo
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
action chain match m 0 0 0 execute store load
Table 47.  Trigger Data 2 Register FieldsThe tdata2 register is a 32-bit read/write register containing the trigger-specific data.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
tdata2
Table 48.  Trigger Info Register FieldsThe tinfo register is a 32-bit read-only register containing information on each possible tdata1.type.
Bit Field
31 30 29 … 18 17 16 15 14 13 … 2 1 0
0 info
Table 49.  Debug Control and Status Register FieldsThe dcsr CSR is a 32-bit read-write register containing information and status during D-mode. This core does not support supervisor or user modes. Thus, any bitfield related to these modes is read-only 0.
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
debugver 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ebreakm 0 0 0 stepie stopcount stoptime cause 0 mprven nmip step prv
Table 50.  Debug Program Counter Register FieldsUpon entry to D-mode, dpc CSR is updated with the virtual address of the next instruction to be executed.
Bit Field
31 30 29 28 27 26 25 ... 6 5 4 3 2 1 0
dpc
Table 51.  Vendor ID Register FieldsThe mvendorid CSR is a 32-bit read-only register that provides the JEDEC manufacturer ID of the provider of the core.
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bank
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bank Offset
Table 52.  Architecture ID Register FieldsThe marchid CSR is a 32-bit read-only register encoding the base microarchitecture of the hart.
Bit Field
31 30 29 28 27 26 25 ... 6 5 4 3 2 1 0
Architecture ID
Table 53.  Implementation ID Register FieldsThe mimpid CSR provides a unique encoding of the version of the processor implementation.
Bit Field
31 30 29 28 27 26 25 ... 6 5 4 3 2 1 0
Implementation
Table 54.  Hardware Thread ID Register FieldsThe mhartid CSR is a 32-bit read-only register that contains the integer ID of the hardware thread running the code
Bit Field
31 30 29 28 27 26 25 ... 6 5 4 3 2 1 0
Hart ID
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