Other Transceiver IP Cores Product Release Notes

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ID 683625
Date 10/31/2016
Public
Document Table of Contents
Document Table of Contents x
1. Other Transceiver IP Cores Product Release Notes
1. Other Transceiver IP Cores Product Release Notes x
1.1. Transceiver PHY Reset Controller IP Core v15.1 Revision History 1.2. Transceiver PHY Reset Controller IP Core v14.1 Revision History 1.3. Transceiver PHY Reset Controller IP Core v14.0 Arria 10 Revision History 1.4. Transceiver PHY Reset Controller IP Core v13.0 Arria 10 Revision History
1. Other Transceiver IP Cores Product Release Notes

1.2. Transceiver PHY Reset Controller IP Core v14.1 Revision History

Table 2.   v14.1 December 2014
Description Impact
Added an optional port pll_cal_busy. To enable pll_cal_busy select Enable pll_cal_busy input port parameter under the TX Channel option in the Reset Controller IP Core parameter editor. If not enabled, then by default, this port is connected to 1'b0. -
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