In ACDS 15.1, the Quartus Prime software includes a modification to Arria 10 designs using transceivers that controls and sequences rx_analogreset and tx_analogreset to transceiver channels. This new sequencing logic is inserted into the design during Quartus Prime compilation.

The Transceiver PHY Reset Controller IP core adds a new parameter (T_TX_ANALOGRESET) for Arria 10 devices. This change requires a modification to all instances of the Transceiver PHY Reset Controller IP core.

Configure the Transceiver PHY Reset Controller IP core with the following parameters for most designs:

T_TX_ANALOGRESET (tx_analogreset duration) : 70000
R_RX_ANALOGRESET (rx_analogreset duration) : 70000
T_TX_DIGITALRESET (tx_digitalreset duration) : 70000

These settings ensure that the new underlying reset sequencer logic has sufficient time to accept the reset inputs from the Transceiver PHY Reset Controller IP core.