F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 7/08/2024
Document Table of Contents

1. About the F-Tile Interlaken Intel® FPGA IP

Updated for:
Intel® Quartus® Prime Design Suite 24.2
IP Version 8.1.0
Interlaken is a high-speed serial communication protocol for chip-to-chip packet transfers. The F-Tile Interlaken IP implements the Interlaken Protocol Specification, v1.2. The IP supports multiple combinations of number of lanes (1 to 12) and lane rates from 6.25 gigabits per second (Gbps) to 106.25 Gbps providing raw bandwidth up to 675 Gbps.

Interlaken provides low I/O count compared to earlier protocols, supporting scalability in both number of lanes and lane speed. Other key features include flow control, low overhead framing, and extensive integrity checking. The Interlaken IP incorporates a physical coding sublayer (PCS), a physical media attachment (PMA), and a media access control (MAC) block.

Figure 1. Typical Interlaken Application

Interlaken look-aside is a scalable protocol that allows interoperability between a datapath device and a look-aside co-processor with packet transfer rates up to 300 Gbps. The IP supports Interlaken look-aside