F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 10/02/2023

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1.5. Round-trip Latency

The following table includes the round-trip latency numbers for specific variants. The latency numbers were measured for the longest logical datapath for two highest lane rate and number of lanes variants, with FIFO level at 50 for the first packet.
Table 7.  Round-trip Latency NumbersThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 23.1
Note: Latency is calculated based on recommended user clock frequency in design example
Transfer Mode Protocol Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes Latency (ns)
Interleaved (Number of segments = 4) Interlaken NRZ FGT 25.78125 12 774.28
PAM4 FGT 53.125 6 1037.14
53.125 12 1043.33
FHT 106.25 3 1045.71
106.25 4 1088.57
Interlaken Look-aside NRZ FGT 25.78125 12 302.86
PAM4 FGT 53.125 6 562.86
FHT 106.25 3 574.29