F-Tile Interlaken Intel® FPGA IP User Guide

Download PDF
ID 683622
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Performance and Resource Utilization 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Analog Parameter Settings 2.5. Reference and System PLL Clock for your IP Design 2.6. Simulating the IP Core 2.7. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Reference and System PLL Clock for your IP Design x
2.5.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Interlaken Look-aside Data Path Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control 4.8. 32-bit Soft CWBIN Counters
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Data Path Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multi-Segment Mode 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multi-Segment Mode x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide

4.7. Out-of-Band Flow Control

The Interlaken IP core design example provides example logic to include the out-of-band flow control functionality. You can find this logic in the following location: <design_example_installation_dir>/example_design/rtl. The RX out-of-band flow control module is called ilk_oob_flow_rx and the TX out-of-band flow control is called ilk_oob_flow_tx. Alternatively, you can design and implement your own custom out-of-band control logic. The optional out-of-band flow control interface conforms to the out-of-band requirements in Section 5.3.4.2, Out-of-Band Flow Control, of the Interlaken Protocol Specification, Revision 1.2. This optional feature is intended for applications that require transmission rate control.

Figure 27. Out-of-Band Flow Control Block Interface

This figure lists the signals on the four interfaces of the out-of-band flow control block.

The out-of-band flow control block is provided as two separate modules that can be connected to the Interlaken IP core and user logic. You can optionally instantiate these blocks in your own custom logic. To enable the use of these out-of-band modules, the signals on the far left side of the figure must be connected to user logic, and the signals on the far right side of the figure should be connected to the complementary flow control blocks of the Interlaken link partner.

You must connect the out-of-band flow control receive and transmit interface signals to device pins.
Table 17.  Out-of-Band Flow Control Block Clocks
Clock Name Interface Direction Recommended Frequency (MHz) Description
rx.fc_clk RX Out-of-band Input 100 Clocks the incoming out‑of‑band flow control interface signals described in the Interlaken specification. This clock is received from an upstream TX out‑of‑band flow control block associated with the Interlaken link partner. The recommended frequency for the RX fc_clk clock is 100 MHz, which is the maximum frequency allowed by the Interlaken specification.
tx.fc_clk TX Out-of-band Output 100 Clocks the outgoing out‑of‑band flow control interface signals described in the Interlaken specification. This clock is generated by the out‑of‑band flow control block and sent to a downstream RX out‑of‑band flow control block associated with the Interlaken link partner. The frequency of this clock must be half the frequency of the double_fc_clk clock. The recommended frequency for the TX fc_clk clock is 100 MHz, which is the maximum frequency allowed by the Interlaken specification.
sys_clk RX Application Input 200 Clocks the outgoing calendar and status information on the application side of the block. The frequency of this clock must be at least double the frequency of the RX input clock fc_clk. Therefore, the recommended frequency for the sys_clk clock is 200 MHz.
double_fc_clk TX Application Input 200 Clocks the incoming calendar and status information on the application side of the block. The frequency of this clock must be double the frequency of the TX output clock fc_clk. Therefore, the recommended frequency for the double_fc_clk clock is 200 MHz.
The transmit out-of-band flow control interface receives calendar and status information, and transmits flow control clock, data, and sync signals. The TX Out-of-Band Flow Control Interface Signals table describes the transmit out-of-band flow control interface signals specified in the Interlaken Protocol Specification, Revision 1.2. The TX Out-of-Band Flow Control Block Signals for Application Use table describes the signals on the application side of the TX out-of-band flow control block.
Table 18.  TX Out-of-Band Flow Control Interface Signals
Signal Name Direction Width (Bits) Description
tx.fc_clk Output 1 Output reference clock to a downstream out-of-band RX block. Clocks the fc_data and fc_sync signals. You must connect this signal to a device pin.
tx.fc_data Output 1 Output serial data pin to a downstream out-of-band RX block. You must connect this signal to a device pin.
tx.fc_sync Output 1 Output sync control pin to a downstream out-of-band RX block. You must connect this signal to a device pin.
Table 19.  TX Out-of-Band Flow Control Block Signals for Application Use
Signal Name Direction Width (Bits) Description
double_fc_clk Input 1 Reference clock for generating the flow control output clock fc_clk. The frequency of the double_fc_clk clock must be double the intended frequency of the TX fc_clk output clock.
double_fc_arst Input 1 Asynchronous reset for the out-of-band TX block.
ena_status Input 1 Enable transmission of the lane status and link status to the downstream out-of-band RX block. If this signal is asserted, the lane and link status information is transmitted on fc_data. If this signal is not asserted, only the calendar information is transmitted on fc_data.
lane_status Input Number of Lanes Lane status to be transmitted to a downstream out-of-band RX block if ena_status is asserted. Width is the number of lanes.
link_status Input 1 Link status to be transmitted to a downstream out-of-band RX block if ena_status is asserted.
calendar Input 16 Calendar status to be transmitted to a downstream out-of-band RX block.
The receive out-of-band flow control interface receives input flow control clock, data, and sync signals and sends out calendar and status information. The RX Out-of-Band Flow Control Interface Signals table describes the receive out-of-band flow control interface signals specified in the Interlaken Protocol Specification, Revision 1.2. The RX Out-of-Band Flow Control Block Signals for Application Use describes the signals on the application side of the RX out-of-band flow control block.
Table 20.  RX Out-of-Band Flow Control Interface Signals
Signal Name Direction Width (Bits) Description
rx.fc_clk Input 1 Input reference clock from an upstream out-of-band TX block. This signal clocks the fc_data and fc_sync signals. You must connect this signal to a device pin.
rx.fc_data Input 1 Input serial data pin from an upstream out-of-band TX block. You must connect this signal to a device pin.
rx.fc_sync Input 1 Input sync control pin from an upstream out-of-band TX block. You must connect this signal to a device pin.
Table 21.  RX Out-of-Band Flow Control Block Signals for Application Use
Signal Name Direction Width (Bits) Description
sys_clk Input 1 Reference clock for capturing RX calendar, lane status, and link status. Frequency must be at least double the frequency of the TX fc_clk input clock.
sys_arst Input 1 Asynchronous reset for the out-of-band RX block.
status_update Output 1 Indicates a new value without CRC4 errors is present on at least one of lane_status or link_status in the current sys_clk cycle. The value is ready to be read by the application logic.
lane_status Output Number of Lanes Lane status bits received from an upstream out-of-band TX block on fc_data. Width is the number of lanes.
link_status Output 1 Link status bit received from an upstream out-of-band TX block on fc_data.
status_error Output 1 Indicates corrupt lane or link status. A new value is present on at least one of lane_status or link_status in the current sys_clk cycle, but the value has at least one CRC4 error.
calendar Output 16 Calendar bits received from an upstream out-of-band TX block on fc_data.
calendar_update Output 1 Indicates a new value without CRC4 errors is present on calendar in the current sys_clk cycle. The value is ready to be read by the application logic.
calendar_error Output 1 Indicates corrupt calendar bits. A new value is present calendar in the current sys_clk cycle, but the value has at least one CRC4 error.
Level Two Title