F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 10/02/2023
Public

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5.1. Clock and Reset Interface Signals

Table 22.  Clock and Reset Interface Signals
Signal Name Width (Bits) I/O Direction Available In Description
pll_ref_clk 1 Input Interlaken and Interlaken Look-aside mode F-tile reference clock source.

Connect to out_refclk_fgt_<n> output of F-Tile Reference and System PLL Clocks Intel FPGA IP core. For more information, refer to System PLL Configuration.

tx_usr_clk 1 Input Interlaken mode Transmit side user data interface clock. The lower frequency of tx_usr_clk increases the latency of data path. You can also connect it to clk_tx_common.
rx_usr_clk 1 Input Interlaken mode Receive side user data interface clock. The lower frequency of rx_usr_clk increases the latency of data path. You can also connect it to clk_rx_common.
clk_tx_common 1 Output Interlaken and Interlaken Look-aside mode Transmit PCS common lane clock driven by the SERDES transmit PLL.
clk_rx_common 1 Output Interlaken and Interlaken Look-aside mode Receive PCS common lane clock driven by CDR in transceiver.

The valid frequencies for clk_rx_common are same as clk_tx_common.

sysclk 1 Input Interlaken and Interlaken Look-aside mode This clock signal is only available in PAM4 IP core variations. Connect to out_systempll_clk_<m> output of F-Tile Reference and System PLL Clocks Intel FPGA IP core. For more information, refer to System PLL Configuration.
mac_clkin 1 Input Interlaken and Interlaken Look-aside mode This clock signal is only available in PAM4 IP core variations. This signal must be driven by a PLL and must use the same clock source that drives the pll_ref_clk.

The frequency for mac_clkin is 395.833 MHz.

mac_pll_locked 1 Input Interlaken and Interlaken Look-aside mode Lock indicator for the PLL that generates mac_clkin.
reset_n 1 Input Interlaken and Interlaken Look-aside mode Active-low asynchronous reset signal for IP only. You must put the IP in reset when resetting the F-tile to prevent IP corruption while waiting for F-tile to be fully in reset.
tx_rst_n 1 Input Interlaken and Interlaken Look-aside mode Active low asynchronous reset for F-tile. This reset drives the tx_desired_state of SRC.
rx_rst_n 1 Input Interlaken and Interlaken Look-aside mode Active low asynchronous reset for F-tile. This reset drives the rx_desired_state of SRC. When you perform a Serial Internal Loopback CPI Command, this reset must be held low until TX is fully out-of-reset.
tx_rst_ack_n 1 Output Interlaken and Interlaken Look-aside mode Active low asynchronous reset acknowledge signal. Indicates that soft reset controller has successfully entered reset mode for TX side and you can now release the tx_rst_n signal. This signal stays low until you release the tx_rst_n signal.
rx_rst_ack_n 1 Output Interlaken and Interlaken Look-aside mode Active low asynchronous reset acknowledge signal. Indicates that soft reset controller has successfully entered reset mode for RX side and you can now release the rx_rst_n signal. This signal stays low until you release the rx_rst_n signal.
tx_usr_srst 1 Output Interlaken and Interlaken Look-aside mode Transmit-side reset output signal. Indicates the transmit side user data interface is under reset. This signal is synchronous with tx_usr_clk.
rx_usr_srst 1 Output Interlaken and Interlaken Look-aside mode Receive-side reset output signal. Indicates the receive side user data interface is under reset. This signal is synchronous with rx_usr_clk.