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4. Functional Description
The F-Tile Interlaken Intel® FPGA IP core supports the following interfaces:
User Data Transfer Interface
The user data transfer interface, also known as application interface, provides up to 256 logical channels of communication to and from the Interlaken link. This interface is similar to the Avalon® Streaming ( Avalon® -ST) interface which supports data bursts or packets, which are carried in the Interlaken meta frame payload.
Interlaken Link Interface
The Interlaken interface complies with the Interlaken Protocol Specification, Revision 1.2. It is the high-speed transceiver interface to an Interlaken link.
The management interface provides access to the Interlaken IP internal status and control registers. This interface does not provide access to the hard PCS registers on the device. This interface complies with the Avalon® Memory-Mapped ( Avalon® -MM) specification defined in the Avalon Interface Specifications.
Transceiver Control Interfaces
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