F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 12/22/2022
Public

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5.5. Reconfiguration Interface Signals

Table 26.  Transceiver Reconfiguration Interface Signals
Signal Name Width (Bits) I/O Direction Available In Description
reconfig_xcvr_clk 1 Input Interlaken and Interlaken Look-aside mode Transceiver reconfiguration interface clock. Supported frequency range 100-250MHz.
reconfig_xcvr_reset 1 Input Active-high synchronous reset. Assert this signal to reset the transceiver reconfiguration interface.
reconfig_xcvr_read 1 Input Read access to the hard PCS registers.
reconfig_xcvr_write 1 Input Write access to the hard PCS registers.
reconfig_xcvr_address 18+5 Input Address to access the hard PCS registers. This signal holds both the hard PCS register offset and the transceiver channel being addressed.
  • 18-bits for address
  • 5-bits for lane selection
reconfig_xcvr_writedata 32 Input When reconfig_write is high, reconfig_writedata holds valid write data.
reconfig_xcvr_readdata 32 Output After user logic asserts the reconfig_read signal, when the IP core deasserts the signal, reconfig_readdata holds valid read data.
reconfig_xcvr_readdatavalid 1 Output Valid signal for reconfig_xcvr_readdata.
reconfig_xcvr_waitrequest 1 Output Busy signal for reconfig_readdata.
reconfig_xcvr_byteenable 4 Input Transceiver reconfiguration byte enable signal.
Table 27.  Interlaken Reconfiguration Interface SignalsThese signals are only available for PAM4 mode.
Signal Name Width (Bits) I/O Direction Available In Description
reconfig_ilk_clk 1 Input Interlaken mode Interlaken reconfiguration interface clock. Supported frequency range 100-250MHz.
reconfig_ilk_reset 1 Input Active-high synchronous reset. Assert this signal to reset the Interlaken reconfiguration interface.
reconfig_ilk_read 1 Input Read access to the Interlaken reconfiguration registers.
reconfig_ilk_write 1 Input Write access to the Interlaken reconfiguration registers.
reconfig_ilk_address 14+3 Input Address to access the Interlaken reconfiguration registers.
  • 14-bits for address
  • 3-bits for FEC selection
reconfig_ilk_writedata 32 Input When reconfig_write is high, reconfig_writedata holds valid write data.
reconfig_ilk_readdata 32 Output After user logic asserts the reconfig_read signal, when the IP core deasserts the signal, reconfig_readdata holds valid read data.
reconfig_ilk_readdatavalid 1 Output Valid signal for reconfig_ilk_readdata.
reconfig_ilk_waitrequest 1 Output Busy signal for reconfig_readdata.
reconfig_ilk_byteenable 4 Input Interlaken reconfiguration byte enable signal.