F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 1/14/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.4. Management Interface Signals

The management interface signals are available for the Avalon® -MM (AVMM) interface.
Table 25.  Management Interface Signals
Signal Name Width (Bits) I/O Direction Description
mm_clk 1 Input Management clock. Clocks the register accesses. It is also used for clock rate monitoring and some analog calibration procedures. You must run this clock at a frequency in the range of 100 MHz–125 MHz.
mm_read 1 Input

Read access to the register ports.

mm_write 1 Input

Write access to the register ports.

mm_addr 16 Input

Address to access the register ports.

mm_rdata 32 Output

When mm_rdata_valid is high, mm_rdata holds valid read data.

mm_rdata_valid 1 Output

Valid signal for mm_rdata.

mm_wdata 32 Input

When mm_write is high, mm_wdata holds valid write data.