Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide

Download PDF
ID 683616
Date 11/06/2017
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide
1. Quick Start Guide x
1.1. Design Components 1.2. Directory Structure 1.3. Generating the Design Example 1.4. Simulating the Design Example 1.5. Compiling the Design Example and Programming the Device 1.6. Installing the Linux Kernel Driver 1.7. Running the Design Example Application
2. Design Example Description x
2.1. Functional Description for the Simple DMA Design Example
2.1. Functional Description for the Simple DMA Design Example x
2.1.1. Serial Data Signals
A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide x
A.1. Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide Revision History
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide

1.4. Simulating the Design Example

Figure 5. Procedure
  1. Change to the testbench simulation directory, pcie_example_design_tb.
  2. Run the simulation script for the simulator of your choice. Refer to the table below.
  3. Analyze the results.
Table 1.  Steps to Run Simulation
Simulator Working Directory Instructions
ModelSim* <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/mentor/
  1. do msim_setup.tcl
  2. ld_debug
  3. run -all
  4. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
VCS* <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/synopsys/vcs
  1. sh vcs_setup.sh USER_DEFINED_SIM_OPTIONS=""
  2. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
NCSim* <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/cadence
  1. sh ncsim_setup.sh USER_DEFINED_SIM_OPTIONS="" USER_DEFINED_ELAB_OPTIONS ="-timescale\ 1ns/1ps"
  2. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
The simple DMA testbench completes the following tasks:
  1. Writes to the Endpoint memory using the DUT Endpoint Avalon® -MM RX master interface.
  2. Reads from Endpoint memory using the DUT Endpoint Avalon® -MM RX master interface.
  3. Verifies the data using the shmem_chk_ok task.
  4. Writes to the Endpoint DMA controller, instructing the DMA controller to perform a MemRd request to the PCIe* address space in host memory.
  5. Writes to the Endpoint DMA controller, instructing the DMA controller to perform a MemWr request to PCIe* address space in host memory. This MemWr uses the data from the previous MemRd.
  6. Verifies the data using the shmem_chk_ok task.

The simulation reports, "Simulation stopped due to successful completion" if no errors occur.

Figure 6. Partial Transcript from Successful Simulation Testbench
Level Two Title