Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide

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ID 683616
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide
1. Quick Start Guide x
1.1. Design Components 1.2. Directory Structure 1.3. Generating the Design Example 1.4. Simulating the Design Example 1.5. Compiling the Design Example and Programming the Device 1.6. Installing the Linux Kernel Driver 1.7. Running the Design Example Application
2. Design Example Description x
2.1. Functional Description for the Simple DMA Design Example
2.1. Functional Description for the Simple DMA Design Example x
2.1.1. Serial Data Signals
A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide x
A.1. Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide Revision History
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide

2.1. Functional Description for the Simple DMA Design Example

The simple DMA design example simulation testbench includes the following components:

  • DUT: The Intel® Stratix® 10 Hard IP for PCI Express Endpoint with the Enable high performance bursting Avalon® -MM slave interface (HPTXS) parameter turned on.
  • PCIE_DMA_CONTROLLER_256: A DMA controller that receives control signals from the DUT rxm_bar2 port. Drives the DUT high performance Avalon® -MM slave interface (hptxs) using its Avalon® -MM write_master interface.
  • MEM1: An on-chip RAM that connects to the DUT RXM_bar0, an Avalon® -MM master interface.
  • MEM2: An on-chip RAM that connects to the PCIE_DMA_CONTROLLER_256 Avalon® -MM read and write master interfaces.
  • A testbench driver that configures the Root Port, Endpoint, writes to Endpoint memory, and programs the simple DMA controller.
  • A testbench monitor that checks expected results.
Figure 7. Simple DMA Design Example
Level Two Title