Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 7/07/2025
Public
Document Table of Contents

6.6.3. Avalon® Streaming Delay Intel® FPGA IP Parameters

Table 169.   Avalon® Streaming Delay Intel® FPGA IP Parameters
Parameter Legal Values Default Value Description
NUMBER_OF_DELAY_CLOCKS 0 to 16 1 Specifies the delay the IP introduces, in clock cycles. Platform Designer supports 0 for some systems where no delay is required.
DATA_WIDTH 1–512 8 The width of the data on the Avalon® streaming data interfaces.
BITS_PER_SYMBOL 1–512 8 The number of bits per symbol for the input and output interfaces. For example, byte-oriented interfaces have 8-bit symbols.
USE_PACKETS On/Off Off On indicates that data packet transfers are supported. Packet support includes the startofpacket, endofpacket, and empty signals.
USE_CHANNEL On/Off Off The option to turn on or off the channel signal.
CHANNEL_WIDTH 0-8 1 The width of the channel signal on the data interfaces. This parameter is disabled when USE_CHANNEL is off.
MAX_CHANNELS 0-255 1 The maximum number of channels that a data interface can support. This parameter is disabled when USE_CHANNEL is off.
USE_ERROR On/Off Off The option to turn on or off use of the error signal.
ERROR_WIDTH 0–31 1 The width of the error signal on the output interfaces. A value of 0 indicates that the error signal is not in use. This parameter is disabled when USE_ERROR is off.
Use synchronous resets On/Off Off Turn on for internal reset synchronization. Turn off to allow asynchronous resets.