Quartus® Prime Pro Edition User Guide: Platform Designer
6.4. Avalon® Data Pattern Checker IP
The Avalon® Data Pattern Checker IP verifies the data on an Avalon® streaming data interface. Optionally, you can format the data as packets, with accompanying start_of_packet and end_of_packet signals.
Altera® recommends a unique value for each instance of the data pattern checker IP core in a system.
The Avalon® Data Pattern Checker IP accepts data via an Avalon® streaming interface and verifies it against a predetermined pattern used by the PRBS generators to produce the data. The Avalon® Data Pattern Checker IP reports any exceptions to the control interface.
You can parameterize multiple aspects of the Avalon® Data Pattern Checker's Avalon® streaming interface, such as the number of error bits, and the data signal width. This IP supports testing components with different interfaces. The Avalon® Data Pattern Checker IP has a throttle register that you set via the Avalon® memory-mapped control interface. The value of the throttle register controls the rate at which data is accepted.
The Avalon® Data Pattern Checker IP detects exceptions and reports them to the control interface via a 32-element deep internal FIFO. Possible exceptions are data error, missing start-of-packet (SOP), missing end-of-packet (EOP), and signaled error.
As each exception occurs, an exception descriptor is pushed into the FIFO. If the same exception occurs more than once consecutively, only one exception descriptor is pushed into the FIFO. All exceptions are ignored when the FIFO is full. Exception descriptors are deleted from the FIFO after they are read by the control and status interface.
Section Content
Avalon Data Pattern Checker IP Input Interface
Avalon Data Pattern Checker IP Control and Status Interface
Avalon Data Pattern Checker IP Supported Data Patterns
Avalon Data Pattern Checker IP Functional Parameters
Avalon Data Pattern Checker IP Software Programming Model
Avalon Data Pattern Checker IP API