Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 7/07/2025
Public
Document Table of Contents

6.4.3. Avalon® Data Pattern Checker IP Supported Data Patterns

The Avalon® Data Pattern Checker IP supports data patterns in following manner, per beat, as table Supported Data Patterns (Binary Encoding) specifies.

When the core is disabled or in idle state, the default pattern generated on the data output is 0×5555 (for 32-bit data width) or 0×55555 (for 40-bit data width). functional parameter allows you to configure the Avalon® Data Pattern Checker IP as a whole system.

Table 138.  Supported Data Patterns (Binary Encoding)
Pattern 32-bit 40-bit
PRBS-7 PRBS in parallel PRBS in parallel
PRBS-15 PRBS in parallel PRBS in parallel
PRBS-23 PRBS in parallel PRBS in parallel
PRBS-31 PRBS in parallel PRBS in parallel
High Frequency 10101010 x 4 1010101010 x 4
Low Frequency 11110000 x 4 1111100000 x 4