Low Latency 40-Gbps Ethernet Intel® FPGA IP User Guide: Stratix® 10

Download PDF
ID 683600
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Core 2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters 3. Getting Started 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives 11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device 12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide
1. About the Low Latency 40G Ethernet Core x
1.1. Stratix® 10 LL 40GbE IP Core Supported Features 1.2. Stratix® 10 LL 40GbE Core Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Stratix® 10 LL 40GbE Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. Stratix® 10 LL 40GbE IP Core Device Speed Grade Support
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the Stratix® 10 LL 40GbE IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench 3.7. Compiling the Full Design and Programming the FPGA
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the Transceiver PLL 3.5.3. Clock Requirements for 40GBASE-KR4/CR4 Variations 3.5.4. Adding the External TX MAC PLL 3.5.5. Placement Settings for the Stratix® 10 Low Latency 40G Ethernet Core
3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench x
3.6.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Stratix® 10 LL 40GbE Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. Stratix® 10 LL 40GbE Core Functional Description x
4.1.1. Stratix® 10 LL 40GbE Core TX MAC Datapath 4.1.2. Stratix® 10 LL 40GbE Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. Stratix® 10 Low Latency 40GBASE-KR4 IP Core Variations
4.1.1. Stratix® 10 LL 40GbE Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC-32) Insertion
4.1.2. Stratix® 10 LL 40GbE Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. Length/Type Field Processing 4.1.2.4. RX CRC Checking and Dynamic Forwarding
4.1.2.3. Length/Type Field Processing x
4.1.2.3.1. Length Checking
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers Signals 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
7. Control, Status, and Statistics Register Descriptions x
7.1. Stratix® 10 LL 40GBASE-KR4/CR4 Registers 7.2. PHY Registers 7.3. TX MAC Registers 7.4. RX MAC Registers 7.5. Statistics Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
9. Ethernet Toolkit Overview x
9.1. Features
1. About the Low Latency 40G Ethernet Core
2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device
12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide

7.4. RX MAC Registers

Table 28.  RX MAC Registers
Addr Name Description Reset Access
0x500 RXMAC_REVID

RX MAC revision ID for Stratix 10 40GbE IP core.

0x0627 2016 RO
0x501 RXMAC_SCRATCH Scratch register available for testing. 0x0000 0000 RW
0x502 RXMAC_NAME_0

First 4 characters of IP core variation identifier string, "40gMACRxCSR".

0x3430 674D

RO
0x503 RXMAC_NAME_1 Next 4 characters of IP core variation identifier string, "ACRx". 0x4143 5278

RO
0x504 RXMAC_NAME_2 Final 4 characters of IP core variation identifier string, "0CSR". The "0" is unprintable. 0x0043 5352

RO
0x506 MAX_RX_SIZE_CONFIG Specifies the maximum frame length available. The MAC asserts l2_rx_error[3] when the length of the received frame exceeds the value of this register.

If the IP core receives an Ethernet frame of size greater than the number of bytes specified in this register, and the IP core includes statistics registers, the IP core increments the 64-bit CNTR_RX_OVERSIZE counter.

0xXXXX 2580 4

RW
0x507 MAC_CRC_CONFIG The RX CRC forwarding configuration register. The following encodings are defined:
  • 1'b0: Remove RX CRC, do not forward it to the RX client interface
  • 1'b1: Retain RX CRC, forward it to the RX client interface
In either case, the IP core checks the incoming RX CRC and flags errors. 		31'hX1'b0 4

RW
0x508 LINK_FAULT

Link Fault Status Register.

  • Bit[0]: Local fault status bit.
  • Bit[1]: Remote fault status bit.

For regular (non-unidirectional) Link Fault, implements IEEE 802.3 BA Ethernet Clause 81.3.4.

For unidirectional Link Fault, implements IEEE 802.3 Ethernet Clause 66.

30'hX2'b00 4

RO
0x50A RX_MAC_CONTROL RX MAC Control Register. The following bits are defined:
  • Bit[4]: Preamble check. Strict SFD checking option to compare each packet preamble to 0x555555555555. This field is available only if you turn on Enable Strict SFD check .
  • Bit[3]: SFD check. Strict SFD checking option to compare each SFD byte to 0x5D. This field is available only if you turn on Enable Strict SFD check .
  • Bit [1]: VLAN detection disabled. This bit is deasserted by default implying VLAN detection is enabled.
30'h0_2'b0X 4 RW
4 X means "Don't Care".
Level Two Title