Low Latency 40-Gbps Ethernet Intel® FPGA IP User Guide: Stratix® 10
ID
683600
Date
5/31/2024
Public
1. About the Low Latency 40G Ethernet Core
2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device
12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Stratix® 10 LL 40GbE IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
5. Reset
Control and Status registers control three parallel soft resets. These soft resets are not self-clearing. Software clears them by writing to the appropriate register. In addition, the IP core has three hard reset signals.
Asserting the external hard reset csr_rst_n returns all Control and Status registers to their original values, except the statistics counters. An additional dedicated reset signal resets the transceiver reconfiguration interface.
Figure 11. Conceptual Overview of General IP Core Reset Logic The three hard resets are top-level ports. The three soft resets are internal signals which are outputs of the PHY_CONFIG register. Software writes the appropriate bit of the PHY_CONFIG to assert a soft reset.
The general reset signals reset the following functions:
- soft_tx_rst, tx_rst_n: Resets the IP core in the TX direction. Resets the TX PCS and TX MAC. This reset leads to deassertion of the tx_lanes_stable output signal.
- soft_rx_rst, rx_rst_n: Resets the IP core in the RX direction. Resets the RX PCS and RX MAC. This reset leads to deassertion of the rx_pcs_ready output signal.
- sys_rst, csr_rst_n: Resets the IP core. Resets the TX and RX MACs, PCS, and transceivers.
Note: csr_rst_n resets the Control and Status registers, except the statistics counters. sys_rst does not reset any Control and Status registers.This reset leads to deassertion of the tx_lanes_stable and rx_pcs_ready output signals.
In addition, the synchronous reconfig_reset signal resets the IP core transceiver reconfiguration interface, an Avalon® memory-mapped interface. Associated clock is the reconfig_clk, which clocks the transceiver reconfiguration interface.
Note: The IP core has a top-level reset_status signal. However, this signal is currently unconnected in the IP core and has no effect. This signal is expected to be deprecated in future Stratix® 10 releases.
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