1. MAX® 10 Analog to Digital Converter Overview
2. MAX® 10 ADC Architecture and Features
3. MAX® 10 ADC Design Considerations
4. MAX® 10 ADC Implementation Guides
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References
6. MAX® 10 Analog to Digital Converter User Guide Archives
7. Document Revision History for the MAX® 10 Analog to Digital Converter User Guide
2.2.1.1. Configuration 1: Standard Sequencer with Avalon-MM Sample Storage
2.2.1.2. Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection
2.2.1.3. Configuration 3: Standard Sequencer with External Sample Storage
2.2.1.4. Configuration 4: ADC Control Core Only
5.4.1. Command Interface of Modular ADC Core and Modular Dual ADC Core
5.4.2. Response Interface of Modular ADC Core and Modular Dual ADC Core
5.4.3. Threshold Interface of Modular ADC Core and Modular Dual ADC Core
5.4.4. CSR Interface of Modular ADC Core and Modular Dual ADC Core
5.4.5. IRQ Interface of Modular ADC Core and Modular Dual ADC Core
5.4.6. Peripheral Clock Interface of Modular ADC Core and Modular Dual ADC Core
5.4.7. Peripheral Reset Interface of Modular ADC Core and Modular Dual ADC Core
5.4.8. ADC PLL Clock Interface of Modular ADC Core and Modular Dual ADC Core
5.4.9. ADC PLL Locked Interface of Modular ADC Core and Modular Dual ADC Core
2.5.2. User-Specified ADC Logic Simulation Output
You can configure the Modular ADC Core or Modular Dual ADC Core IP core to output user-specified values in the logic simulation for each ADC channel except the TSD channel.
If you enable this feature, you must provide a simulation stimulus input file for each ADC channel that you enable. The logic simulation reads the input file for each channel and outputs the value of the current sequence. Once the simulation reaches the end of the file, it repeats from the beginning of the sequence.
The stimulus input file is a plain text file that contains two columns of numbers:
- The first column of numbers is ignored by the simulation model. You can use any values that you want such as time or sequence. The actual data sequencing is based on the text rows.
- The second column contains the voltage values.
The ADC IP core automatically converts each voltage value to a 12-bit digital value based on the reference voltage you specify in the IP core parameter settings.
Figure 23. Simulation Output Example, One Channel Enabled
Figure 24. Simulation Output Example, Two Channels Enabled