1. MAX® 10 Analog to Digital Converter Overview
2. MAX® 10 ADC Architecture and Features
3. MAX® 10 ADC Design Considerations
4. MAX® 10 ADC Implementation Guides
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References
6. MAX® 10 Analog to Digital Converter User Guide Archives
7. Document Revision History for the MAX® 10 Analog to Digital Converter User Guide
2.2.1.1. Configuration 1: Standard Sequencer with Avalon-MM Sample Storage
2.2.1.2. Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection
2.2.1.3. Configuration 3: Standard Sequencer with External Sample Storage
2.2.1.4. Configuration 4: ADC Control Core Only
5.4.1. Command Interface of Modular ADC Core and Modular Dual ADC Core
5.4.2. Response Interface of Modular ADC Core and Modular Dual ADC Core
5.4.3. Threshold Interface of Modular ADC Core and Modular Dual ADC Core
5.4.4. CSR Interface of Modular ADC Core and Modular Dual ADC Core
5.4.5. IRQ Interface of Modular ADC Core and Modular Dual ADC Core
5.4.6. Peripheral Clock Interface of Modular ADC Core and Modular Dual ADC Core
5.4.7. Peripheral Reset Interface of Modular ADC Core and Modular Dual ADC Core
5.4.8. ADC PLL Clock Interface of Modular ADC Core and Modular Dual ADC Core
5.4.9. ADC PLL Locked Interface of Modular ADC Core and Modular Dual ADC Core
5.4.2. Response Interface of Modular ADC Core and Modular Dual ADC Core
The response interface is an Avalon-ST type interface that does not support backpressure. To avoid overflow condition at the source port, implement sink ports with response data process time that is fast enough, or with enough buffers storage.
Signal | Width (Bit) | Description |
---|---|---|
valid | 1 | Indication from the source port that current transfer is valid. |
channel | 5 | Indicates the ADC channel to which the ADC sampling data corresponds for the current response.
|
data | 12 or 24 | ADC sampling data:
|
startofpacket | 1 | Indication from the source port that current transfer is the start of packet. For altera_adc_control core implementation, the source of this signal is from the corresponding command interface. |
endofpacket | 1 | Indication from the source port that current transfer is the end of packet. For altera_adc_control core implementation, the source of this signal is from the corresponding command interface. |