1. MAX® 10 Analog to Digital Converter Overview
2. MAX® 10 ADC Architecture and Features
3. MAX® 10 ADC Design Considerations
4. MAX® 10 ADC Implementation Guides
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References
6. MAX® 10 Analog to Digital Converter User Guide Archives
7. Document Revision History for the MAX® 10 Analog to Digital Converter User Guide
2.2.1.1. Configuration 1: Standard Sequencer with Avalon-MM Sample Storage
2.2.1.2. Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection
2.2.1.3. Configuration 3: Standard Sequencer with External Sample Storage
2.2.1.4. Configuration 4: ADC Control Core Only
5.4.1. Command Interface of Modular ADC Core and Modular Dual ADC Core
5.4.2. Response Interface of Modular ADC Core and Modular Dual ADC Core
5.4.3. Threshold Interface of Modular ADC Core and Modular Dual ADC Core
5.4.4. CSR Interface of Modular ADC Core and Modular Dual ADC Core
5.4.5. IRQ Interface of Modular ADC Core and Modular Dual ADC Core
5.4.6. Peripheral Clock Interface of Modular ADC Core and Modular Dual ADC Core
5.4.7. Peripheral Reset Interface of Modular ADC Core and Modular Dual ADC Core
5.4.8. ADC PLL Clock Interface of Modular ADC Core and Modular Dual ADC Core
5.4.9. ADC PLL Locked Interface of Modular ADC Core and Modular Dual ADC Core
5.6. ADC HAL Device Driver for Nios® Processor
The Modular ADC Core and Modular Dual ADC Core IP core provides a HAL device driver. You can integrate the device driver into the HAL system library for Nios® processor systems.
The IP cores provide software files that define low-level access to the hardware. You can use the macros definition and functions in the software files to initialize the cores.
- altera_modular_adc_sequencer_regs.h—this file defines the register map for the sequencer core. It provides symbolic constants to access the low-level hardware.
- altera_modular_adc_sample_store_regs.h—this file defines the register for sample storage core. It provides symbolic constants to access the low-level hardware.
- altera_modular_adc.h or altera_modular_dual_adc.h—include this file into your application. It automatically includes the other header files and defines additional functions.
- altera_modular_adc.c or altera_modular_dual_adc.c—this file implements helper functions that are defined in the header file.
In the same design, there can only be a single type of IP core, either Modular ADC Core or Modular Dual ADC Core IP.
In Quartus® Prime Standard Edition software version 22.1, you need to apply the following software settings based on the IP core configuration (Core Variant).
- All instantiated IP core(s) apply Standard sequencer with external sample storage.
- Enable external_sample_storage in BSP Editor > BSP Driver tab.
- Instantiated IP cores have different Core Variant.
- Enable different_sample_storage in BSP Editor > BSP Driver tab.
- Modify alt_sys_init.c
- For Avalon-MM sample storage (_CORE_VARIANT = 0 or 1),
Change ALTERA_MODULAR_ADC_INSTANCE to ALTERA_MODULAR_ADC_INSTANCE_AVL_MEM
Change ALTERA_MODULAR_ADC_INIT to ALTERA_MODULAR_ADC_INIT_AVL_MEM - For external sample storage (_CORE_VARIANT = 2),
Change ALTERA_MODULAR_ADC_INSTANCE to ALTERA_MODULAR_ADC_INSTANCE_EXT
Change ALTERA_MODULAR_ADC_INIT to ALTERA_MODULAR_ADC_INIT_EXT
- For Avalon-MM sample storage (_CORE_VARIANT = 0 or 1),
Note: The value of _CORE_VARIANT can be found in system.h.